IEEE Journal on Exploratory Solid-State Computational Devices and Circuits最新文献_第5页

A Nonvolatile Compute-in-Memory Macro Using Voltage-Controlled MRAM and In Situ Magnetic-to-Digital Converter 使用压控MRAM和原位磁-数转换器的非易失性内存宏

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2023-03-17 DOI: 10.1109/JXCDC.2023.3258431

Vinod Kurian Jacob;Jiyue Yang;Haoran He;Puneet Gupta;Kang L Wang;Sudhakar Pamarti

{"title":"A Nonvolatile Compute-in-Memory Macro Using Voltage-Controlled MRAM and In Situ Magnetic-to-Digital Converter","authors":"Vinod Kurian Jacob;Jiyue Yang;Haoran He;Puneet Gupta;Kang L Wang;Sudhakar Pamarti","doi":"10.1109/JXCDC.2023.3258431","DOIUrl":"10.1109/JXCDC.2023.3258431","url":null,"abstract":"Compute-in-memory (CIM) accelerator has become a popular solution to achieve high energy efficiency for deep learning applications in edge devices. Recent works have demonstrated CIM macros using nonvolatile memories [spin transfer torque (STT)-MRAM and resistive random access memory (RRAM)] to take advantages of their nonvolatility and high density. However, effective computation dynamic range is far lower than their static random access memory (SRAM)-CIM counterparts due to low device ON/ OFF ratio. In this work, we combine a nonvolatile memory based on a voltage-controlled magnetic tunneling junction (VC-MTJ) device, called voltage-controlled MRAM or VC-MRAM, and accurate switched-capacitor-based CIM using a novel in situ magnetic-to-digital converter (MDC). The VC-MTJ device has demonstrated \u0000<inline-formula> <tex-math>$10times $ </tex-math></inline-formula>\u0000 lower write energy and switching time compared to STT-MRAM device and has comparable density, read energy, and read latency. The in situ MDCs embedded inside each VC-MRAM row convert magnetically stored weight information to CMOS logic levels and enable switched-capacitor-based multiply–accumulate (MAC) operation with accuracy comparable to the state-of-the-art SRAM-CIM. This article describes the schematic and layout level design of a VC-MRAM CIM macro in 28 nm. This is the first nonvolatile CIM design to enable analog MAC computation with 256 parallel rows turned ON simultaneously without degradation in dynamic range (< 1 LSB). Detailed circuit simulations including experimentally validated VC-MTJ compact models show \u0000<inline-formula> <tex-math>$1.5times $ </tex-math></inline-formula>\u0000 higher energy efficiency and \u0000<inline-formula> <tex-math>$2times $ </tex-math></inline-formula>\u0000 higher density compared to the state-of-the-art SRAM-based CIM.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2023-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/10138050/10075423.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41359420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A High-Parallelism RRAM-Based Compute-In-Memory Macro With Intrinsic Impedance Boosting and In-ADC Computing 基于内禀阻抗增强和adc内计算的高并行rram内存宏

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2023-03-14 DOI: 10.1109/JXCDC.2023.3255788

Tian Xie;Shimeng Yu;Shaolan Li

引用次数: 1

A Full-Stack View of Probabilistic Computing With p-Bits: Devices, Architectures, and Algorithms 概率计算的全栈视图与p位:设备，架构和算法

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2023-03-14 DOI: 10.1109/JXCDC.2023.3256981

Shuvro Chowdhury;Andrea Grimaldi;Navid Anjum Aadit;Shaila Niazi;Masoud Mohseni;Shun Kanai;Hideo Ohno;Shunsuke Fukami;Luke Theogarajan;Giovanni Finocchio;Supriyo Datta;Kerem Y. Camsari

{"title":"A Full-Stack View of Probabilistic Computing With p-Bits: Devices, Architectures, and Algorithms","authors":"Shuvro Chowdhury;Andrea Grimaldi;Navid Anjum Aadit;Shaila Niazi;Masoud Mohseni;Shun Kanai;Hideo Ohno;Shunsuke Fukami;Luke Theogarajan;Giovanni Finocchio;Supriyo Datta;Kerem Y. Camsari","doi":"10.1109/JXCDC.2023.3256981","DOIUrl":"10.1109/JXCDC.2023.3256981","url":null,"abstract":"The transistor celebrated its 75th birthday in 2022. The continued scaling of the transistor defined by Moore’s law continues, albeit at a slower pace. Meanwhile, computing demands and energy consumption required by modern artificial intelligence (AI) algorithms have skyrocketed. As an alternative to scaling transistors for general-purpose computing, the integration of transistors with unconventional technologies has emerged as a promising path for domain-specific computing. In this article, we provide a full-stack review of probabilistic computing with p-bits as a representative example of the energy-efficient and domain-specific computing movement. We argue that p-bits could be used to build energy-efficient probabilistic systems, tailored for probabilistic algorithms and applications. From hardware, architecture, and algorithmic perspectives, we outline the main applications of probabilistic computers ranging from probabilistic machine learning (ML) and AI to combinatorial optimization and quantum simulation. Combining emerging nanodevices with the existing CMOS ecosystem will lead to probabilistic computers with orders of magnitude improvements in energy efficiency and probabilistic sampling, potentially unlocking previously unexplored regimes for powerful probabilistic algorithms.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2023-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/10138050/10068500.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41667070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Oscillator-Inspired Dynamical Systems to Solve Boolean Satisfiability 求解布尔可满足性的振子激励动力系统

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2023-01-31 DOI: 10.1109/JXCDC.2023.3241045

Mohammad Khairul Bashar;Zongli Lin;Nikhil Shukla

引用次数: 3

Dynamical System-Based Computational Models for Solving Combinatorial Optimization on Hypergraphs 基于动力学系统的超图组合优化计算模型

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2023-01-09 DOI: 10.1109/JXCDC.2023.3235113

Mohammad Khairul Bashar;Antik Mallick;Avik W. Ghosh;Nikhil Shukla

{"title":"Dynamical System-Based Computational Models for Solving Combinatorial Optimization on Hypergraphs","authors":"Mohammad Khairul Bashar;Antik Mallick;Avik W. Ghosh;Nikhil Shukla","doi":"10.1109/JXCDC.2023.3235113","DOIUrl":"10.1109/JXCDC.2023.3235113","url":null,"abstract":"The intrinsic energy minimization in dynamical systems offers a valuable tool for minimizing the objective functions of computationally challenging problems in combinatorial optimization. However, most prior works have focused on mapping such dynamics to combinatorial optimization problems whose objective functions have quadratic degree [e.g., maximum cut (MaxCut)]; such problems can be represented and analyzed using graphs. However, the work on developing such models for problems that need objective functions with degree greater than two, and subsequently, entail the use of hypergraph data structures, is relatively sparse. In this work, we develop dynamical system-inspired computational models for several such problems. Specifically, we define the “energy function” for hypergraph-based combinatorial problems ranging from Boolean Satisfiability (SAT) and its variants to integer factorization, and subsequently, define the resulting system dynamics. We also show that the design approach is applicable to optimization problems with quadratic degree, and use it to develop a new dynamical system formulation for minimizing the Ising Hamiltonian. Our work not only expands on the scope of problems that can be directly mapped to, and solved using physics-inspired models, but also creates new opportunities to design high-performance accelerators for solving combinatorial optimization.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2023-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/10138050/10011425.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48914151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Random Bitstream Generation Using Voltage-Controlled Magnetic Anisotropy and Spin Orbit Torque Magnetic Tunnel Junctions 利用压控磁各向异性和自旋轨道转矩磁隧道结产生随机比特流

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-23 DOI: 10.1109/JXCDC.2022.3231550

Samuel Liu;Jaesuk Kwon;Paul W. Bessler;Suma G. Cardwell;Catherine Schuman;J. Darby Smith;James B. Aimone;Shashank Misra;Jean Anne C. Incorvia

{"title":"Random Bitstream Generation Using Voltage-Controlled Magnetic Anisotropy and Spin Orbit Torque Magnetic Tunnel Junctions","authors":"Samuel Liu;Jaesuk Kwon;Paul W. Bessler;Suma G. Cardwell;Catherine Schuman;J. Darby Smith;James B. Aimone;Shashank Misra;Jean Anne C. Incorvia","doi":"10.1109/JXCDC.2022.3231550","DOIUrl":"10.1109/JXCDC.2022.3231550","url":null,"abstract":"Probabilistic computing using random number generators (RNGs) can leverage the inherent stochasticity of nanodevices for system-level benefits. Device candidates for this application need to produce highly random “coinflips” while also having tunable biasing of the coin. The magnetic tunnel junction (MTJ) has been studied as an RNG due to its thermally-driven magnetization dynamics, often using spin transfer torque (STT) current amplitude to control the random switching of the MTJ free layer (FL) magnetization, here called the stochastic write method. There are additional knobs to control the MTJ-RNG, including voltage-controlled magnetic anisotropy (VCMA) and spin orbit torque (SOT), and there is a need to systematically study and compare these methods. We build an analytical model of the MTJ to characterize using VCMA and SOT to generate random bit streams. The results show that both methods produce high-quality, uniformly distributed bitstreams. Biasing the bitstreams using either STT current or an applied magnetic field shows a sigmoidal distribution versus bias amplitude for both VCMA and SOT, compared to less sigmoidal for stochastic write. The energy consumption per sample is calculated to be 0.1 pJ (SOT), 1 pJ (stochastic write), and 20 pJ (VCMA), revealing the potential energy benefit of using SOT and showing using VCMA may require higher damping materials. The generated bitstreams are then applied to two tasks: generating an arbitrary probability distribution and using the MTJ-RNGs as stochastic neurons to perform simulated annealing, where both VCMA and SOT methods show the ability to effectively minimize the system energy with a small delay and low energy. These results show the flexibility of the MTJ as a true RNG and elucidate design parameters for optimizing the device operation for applications.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2022-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9998452/09998481.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41722839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

High-Density Spin–Orbit Torque Magnetic Random Access Memory With Voltage-Controlled Magnetic Anisotropy/Spin-Transfer Torque Assist 具有电压控制磁各向异性/自旋传递转矩辅助的高密度自旋轨道转矩磁随机存取存储器

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-20 DOI: 10.1109/JXCDC.2022.3230925

Piyush Kumar;Azad Naeemi

引用次数: 1

Self-Reset Schemes for Magnetic Domain Wall-Based Neuron 基于磁畴壁的神经元自复位方案

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-08 DOI: 10.1109/JXCDC.2022.3227774

Debasis Das;Xuanyao Fong

引用次数: 1

Review of Magnetic Tunnel Junctions for Stochastic Computing 随机计算中磁隧道结的研究进展

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-08 DOI: 10.1109/JXCDC.2022.3227062

Brandon R. Zink;Yang Lv;Jian-Ping Wang

引用次数: 6

INFORMATION FOR AUTHORS 作者信息

IF 2.4

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-01 DOI: 10.1109/JXCDC.2022.3231761

引用次数: 0