IEEE Journal on Exploratory Solid-State Computational Devices and Circuits最新文献_第4页

Nanoelectromechanically Gated Gain Cell eDRAM 纳米机电门控增益单元eDRAM

IF 3.1

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-10-06 DOI: 10.1109/JXCDC.2026.3717204

Collin P. Finnan;Choong-Ho Rhee;Tahir Ghani;Tsu-Jae King-Liu

{"title":"Nanoelectromechanically Gated Gain Cell eDRAM","authors":"Collin P. Finnan;Choong-Ho Rhee;Tahir Ghani;Tsu-Jae King-Liu","doi":"10.1109/JXCDC.2026.3717204","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3717204","url":null,"abstract":"The memory wall and the slowdown of static random access memory (SRAM) scaling have renewed interest in gain-cell embedded dynamic random access memory (DRAM). While gain cells offer high density and energy efficiency, they suffer from limited retention, parasitic coupling, and the need for boosted write voltages. This work introduces a nanoelectromechanically gated gain cell for embedded DRAM. The simulated cell eliminates subthreshold leakage and write disturb from parasitic capacitance present in conventional 2T and 3T gain cells, significantly improving retention. In addition, the proposed cell has a write port implemented in back-end-of-line layers to conserve cell layout area relative to transistor-only implementations. A cell size of <inline-formula> <tex-math>$0.072~mu $ </tex-math></inline-formula>m2 is projected for a 2 nm process technology to provide approximately <inline-formula> <tex-math>$3times $ </tex-math></inline-formula> higher cell density than SRAM. Using SPICE simulation, the proposed cell exhibits a retention time of 300 ms at <inline-formula> <tex-math>$125~^{circ } $ </tex-math></inline-formula>C while maintaining sub-1 ns read latency in a <inline-formula> <tex-math>$256~times ~128$ </tex-math></inline-formula> array with significantly smaller static power than SRAM. The proposed bit cell operates at CMOS-compatible voltages and requires minimal process modification from a standard CMOS foundry process, introducing no novel materials.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"223-230"},"PeriodicalIF":3.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11721447","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149130945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Device–Circuit–System Co-Design of Reconfigurable Oxide–Semiconductor 2T Nonvolatile Gain-Cell Memory and Sandwich-3-D LLM Accelerator 可重构氧化半导体2T非易失增益单元存储器与三明治三维LLM加速器的器件-电路-系统协同设计

IF 3.1

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-10-06 DOI: 10.1109/JXCDC.2026.3740041

Luqi Zheng;Chang Niu;Shuting Du;Sumi Lee;Amir Massah Bavani;Zehao Lin;Peide D. Ye;Haitong Li

{"title":"Device–Circuit–System Co-Design of Reconfigurable Oxide–Semiconductor 2T Nonvolatile Gain-Cell Memory and Sandwich-3-D LLM Accelerator","authors":"Luqi Zheng;Chang Niu;Shuting Du;Sumi Lee;Amir Massah Bavani;Zehao Lin;Peide D. Ye;Haitong Li","doi":"10.1109/JXCDC.2026.3740041","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3740041","url":null,"abstract":"In this work, we present an oxide–semiconductor (OS)-based 2T nonvolatile gain-cell (NVGC) memory and a “sandwich 3-D” stacking scheme, co-designed using atomic layer deposition (ALD) InOx oxide–semiconductor FETs (OSFETs) and OS-ferroelectric FETs (FeFETs), for efficient large language model (LLM) acceleration. The new 2T-NVGC enables native, in-memory reconfiguration of static/dynamic kernels for transformers and context-switching workloads, while realizing efficient floating point (FP)/integer (INT) compute-in-memory (CIM). With full-stack, cross-layer co-designs, we present the first complete mixed-signal physical design implementation of an OS-on-CMOS 3D-integrated circuit (IC) with 32.9 TOPS/W energy efficiency and 102.4 TOPS/mm2 compute density. The post-3D-layout simulations calibrated with device experiments demonstrate that the 3D-NVGC LLM accelerator delivers a <inline-formula> <tex-math>$52.3times $ </tex-math></inline-formula> gain in holistic system efficiency over planar CMOS-based and a <inline-formula> <tex-math>$3.2times $ </tex-math></inline-formula> gain over 3-D dynamic random-access memory (DRAM)-based solutions, respectively.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"240-248"},"PeriodicalIF":3.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11719665","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149188222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Antiferromagnetic Programmable Neuron: Structure, Training, and Pattern Recognition Applications 反铁磁可编程神经元：结构、训练和模式识别应用

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2025-11-17 DOI: 10.1109/JXCDC.2025.3633490

I. Sotnyk;O. Prokopenko

{"title":"Antiferromagnetic Programmable Neuron: Structure, Training, and Pattern Recognition Applications","authors":"I. Sotnyk;O. Prokopenko","doi":"10.1109/JXCDC.2025.3633490","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3633490","url":null,"abstract":"Artificial neurons based on antiferromagnetic (AFM) spin Hall oscillators (SHOs) are promising elements for creating ultrafast, energy-efficient neuromorphic computing systems. These structures can generate picosecond spikes in response to dc and ac electric currents, thereby mimicking the reaction of biological neurons to an external stimulus. However, conventional AFM neurons have only one input, which significantly limits their applications. In this article, we propose an approach to the implementation of a programmable artificial neuron (P-neuron) based on conventional AFM neurons in the form of a simple, two-layer neural network. Each neuron in the first layer has an independent input, and all of their outputs are connected to a single main neuron in the second layer. This configuration allows the sensitivity of system to individual input signals to be changed independently and in real time by regulating the dc current applied to the first-layer neurons, which makes it possible to program the entire P-neuron structure. In addition, the P-neuron demonstrates the ability for controlled training. We demonstrate that a multi-input P-neuron can successfully classify small images (<inline-formula> <tex-math>$5times 5$ </tex-math></inline-formula> pixels) of English alphabet symbols. Recognition is based on analyzing the time characteristics of the output neuron signal and comparing them with reference samples. We believe that the obtained results are important for the development and optimization of ultrafast neural network based on AFM nanostructures and AFM spintronic devices capable of generating and processing (sub)terahertz-frequency signals.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"9-17"},"PeriodicalIF":2.7,"publicationDate":"2025-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11250656","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145969438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Integrated Spatiotemporal Multiscale- Multiphysics-Uncertainty Simulation for Controlling Variability in RRAM Devices 集成时空多尺度-多物理场-不确定性模拟用于控制RRAM器件的可变性

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2025-11-14 DOI: 10.1109/JXCDC.2025.3633067

Ziyan Liao;Zhiheng Huang;Min Xiao;Yuezhong Meng;Hui Yan;Yang Liu

{"title":"Integrated Spatiotemporal Multiscale- Multiphysics-Uncertainty Simulation for Controlling Variability in RRAM Devices","authors":"Ziyan Liao;Zhiheng Huang;Min Xiao;Yuezhong Meng;Hui Yan;Yang Liu","doi":"10.1109/JXCDC.2025.3633067","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3633067","url":null,"abstract":"Resistive random access memory (RRAM) is a leading candidate for next-generation nonvolatile memory and neuromorphic computing. However, its performance is limited by inherent switching variability and uncertainties in spatiotemporal multiscale materials and processes. This study integrates multiphysics and multiscale modeling with uncertainty quantification (UQ) to systematically address these limitations and reduce uncertainties. UQ identifies critical inputs that govern key performance metrics, including the<sc>ON/<sc>OFF ratio, forming voltage, and power consumption, reducing their statistical distributions with the probabilities of reliability analysis over 92%. The phase field model (PFM) captures the morphological evolution of conductive filament (CF) and, by incorporating a second-order time derivative for ion diffusion, reveals the impact of morphological fluctuations governing RRAM behavior. Drift diffusion simulations further demonstrate that bilayer structures confine CF fractures to the HfO2 layer through interfacial constraints. This modeling framework provides a systematic approach to mitigate variability and improve the design and reliability of RRAM devices.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"1-8"},"PeriodicalIF":2.7,"publicationDate":"2025-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11248831","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145969437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Energy-Efficient Logic-in-Memory and Neuromorphic Computing in Raised Source and Drain MOSFETs 提高源极和漏极mosfet的高能效内存逻辑和神经形态计算

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2025-11-07 DOI: 10.1109/JXCDC.2025.3630217

Md. Hasan Raza Ansari;Bashayr Alqahtani;Naveen Kumar;Vihar Georgiev;Nazek El-Atab

{"title":"Energy-Efficient Logic-in-Memory and Neuromorphic Computing in Raised Source and Drain MOSFETs","authors":"Md. Hasan Raza Ansari;Bashayr Alqahtani;Naveen Kumar;Vihar Georgiev;Nazek El-Atab","doi":"10.1109/JXCDC.2025.3630217","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3630217","url":null,"abstract":"This work highlights the potential application of raised source and drain (RSD) MOSFETs-based charge trapping memory (CTM) for next-generation computing applications. This simulation study presents a double-gate (DG)-RSD MOSFET technology with a short gate length (50 nm) to significantly improve the performance of logic-in-memory (LIM) and neuromorphic computing (NC) systems. By taking advantage of the superior electrostatic control and reduced parasitic resistance provided by RSD MOSFETs, this work aims to reduce energy consumption for LIM and NC applications. The CTM operation is based on the Fowler–Nordheim (FN) tunneling mechanism, performing 16 Boolean logic functions in two steps: program (PGM) and read operations, including <sc>or, <sc>and, <sc>nor, <sc>nand, <sc>xor, and <sc>xnor. Furthermore, the device shows synapse capability by mimicking long-term potentiation (LTP) and depression long-term depression (LTD) while achieving good linearity and symmetricity between the conductance values. The results reveal that energy consumption for LIM is ~21.4 and ~68.9 fJ for the NC application. This simulation result also demonstrates a high level of accuracy of 88.19%, with less than a 2.04% difference compared to software-based neural networks (90.23%). These multifunctional capabilities of DG-RSD-based CTM highlight the potential application for next-generation computing.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"197-204"},"PeriodicalIF":2.7,"publicationDate":"2025-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11232511","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145560776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Integrating Atomistic Insights With Circuit Simulations via Transformer-Driven Symbolic Regression 通过变压器驱动的符号回归集成原子洞察与电路模拟

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2025-10-23 DOI: 10.1109/JXCDC.2025.3624662

Md Rahatul Islam Udoy;Jack Hutchins;Shamiul Alam;Catherine Schuman;Ahmedullah Aziz

{"title":"Integrating Atomistic Insights With Circuit Simulations via Transformer-Driven Symbolic Regression","authors":"Md Rahatul Islam Udoy;Jack Hutchins;Shamiul Alam;Catherine Schuman;Ahmedullah Aziz","doi":"10.1109/JXCDC.2025.3624662","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3624662","url":null,"abstract":"This article introduces a framework that establishes a cohesive link between the first principles-based simulations and circuit-level analyses using a machine learning-based compact modeling platform. Starting with atomistic simulations, the framework examines the microscopic details of material behavior, forming the foundation for later stages. The generated datasets, with molecular insights, are processed using machine learning (ML) algorithms to identify complex patterns and relationships. As these machine-learning models develop, they become tools for predicting behaviors beyond the reach of conventional modeling and simulation methods. Applied to circuit simulation, the framework improves understanding of electrical interactions, enhancing accuracy and speeding up design automation. As a proof of concept, we perform first principles-based simulations of the graphene nanoribbon field effect transistor (GNRFET), an exploratory device, and create a symbolic-regression-based ML model that can readily be integrated into advanced circuit simulation. This framework presents a template offering a unified approach that synergizes the strengths of first principles-based simulations and circuit-level design tools.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"179-187"},"PeriodicalIF":2.7,"publicationDate":"2025-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11215792","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A SPICE-Compatible Compact Model of Ferroelectric Diode 兼容spice的铁电二极管紧凑模型

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2025-10-23 DOI: 10.1109/JXCDC.2025.3624212

Musaib Rafiq;Mohammad Sajid Nazir;Ateeb Naseer;Yogesh Singh Chauhan;Shubham Sahay

引用次数: 0

Impact of Aging, Self-Heating, and Parasitics Effects on NSFET and CFET 老化、自热和寄生效应对NSFET和CFET的影响

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2025-10-23 DOI: 10.1109/JXCDC.2025.3624653

Swati Deshwal;Sufia Shahin;Anirban Kar;Yogesh S. Chauhan;Hussam Amrouch

{"title":"Impact of Aging, Self-Heating, and Parasitics Effects on NSFET and CFET","authors":"Swati Deshwal;Sufia Shahin;Anirban Kar;Yogesh S. Chauhan;Hussam Amrouch","doi":"10.1109/JXCDC.2025.3624653","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3624653","url":null,"abstract":"This work presents a comparative analysis of complementary field-effect transistor (CFET) and nanosheet FET (NSFET) architectures, with a focus on self-heating effects (SHEs), negative bias temperature instability (NBTI), hot carrier degradation (HCD), and the impact of back-end-of-line (BEOL) parasitics on standard cell performance. NBTI degradation is modeled using a framework combining reaction–diffusion (RD) and reaction–drift–diffusion (RDD) mechanisms in TCAD. BEOL parasitics are extracted using TCAD-generated structures. Both the CFET and NSFET exhibit similar degradation behavior under NBTI stress. However, CFETs show more pronounced degradation due to HCD, primarily driven by stronger SHE. Next, we simulate CFET- and NSFET-based 3-D inverters and SRAM structures in TCAD, with BEOL interconnects up to M3 level, to study the impact of parasitics on the circuit performance. Meanwhile, CFETs offer ~50% area savings at the standard cell level and lower parasitics, leading to a 42% improvement in inverter propagation delay. The SRAM cells based on CFETs are also evaluated and compared against NSFET in terms of area, noise margins, and performance. The CFET SRAM cell provides area gain along with faster and more stable write operations, providing a potential advantage in high-performance applications compared to NSFET.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"188-196"},"PeriodicalIF":2.7,"publicationDate":"2025-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11215725","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Quantum Field Theory Model for Spin-Based Devices Using 2-D van der Waals Materials 二维范德华材料自旋基器件的量子场论模型

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2025-10-22 DOI: 10.1109/JXCDC.2025.3624217

Axel I. Saenz Rodriguez;Oksana Ostroverkhova;Pallavi Dhagat

{"title":"Quantum Field Theory Model for Spin-Based Devices Using 2-D van der Waals Materials","authors":"Axel I. Saenz Rodriguez;Oksana Ostroverkhova;Pallavi Dhagat","doi":"10.1109/JXCDC.2025.3624217","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3624217","url":null,"abstract":"We explore the effects of layered geometries of 2-D quantum spin systems as a method to tune and control material properties for spintronic devices. We analyze the dispersion relation of a 2-D quantum spin system with a shifted bilayer square lattice through the linear spin wave (LSW) approximation of quantum field theory (QFT). Inspired by recent interest in 2-D van der Waals (vdW) magnetic materials, we consider both short-range interactions given by nearest-neighbor intralayer ferromagnetic and interlayer antiferromagnetic spin-exchange interactions and long-range dipole–dipole interactions. This case, along with lattice shifts, has not been treated in the literature via LSW theory. Computations show the gap in the frequencies for the two lowest-energy magnon modes at zero wavenumber that depend on the horizontal and vertical layer shifts. The frequency gap is attributed to the long-range dipole interaction with the gap becoming more sensitive to the horizontal layer shifts for small layer separation. Our general framework is suitable for numerical computations of a wide collection of 2-D lattice models and presents an essential first step toward a comprehensive model that can incorporate quantum effects leading to quantifiable predictions of additional physical properties, for example, spin coherence length and damping, of interest for engineering of spintronic devices.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"171-178"},"PeriodicalIF":2.7,"publicationDate":"2025-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11214338","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comprehensive Device to System Co-Design for SOT-MRAM at the 7 nm Node 7纳米节点SOT-MRAM综合器件系统协同设计

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2025-10-14 DOI: 10.1109/JXCDC.2025.3621279

Piyush Kumar;Da Eun Shim;Azad Naeemi

{"title":"Comprehensive Device to System Co-Design for SOT-MRAM at the 7 nm Node","authors":"Piyush Kumar;Da Eun Shim;Azad Naeemi","doi":"10.1109/JXCDC.2025.3621279","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3621279","url":null,"abstract":"This work presents a comprehensive spin-orbit torque (SOT)-based magnetic random access memory (MRAM) design at the 7 nm technology node, spanning from device-level characteristics to system-level power performance area (PPA). At the device level, we show the tradeoffs among the write current, error rate, and time, based on mircomagnetic simulations. Based on ASAP7 PDK design rules, we create the bit-cell and peripheral layouts for SOT-MRAM and design the entire array. In addition, we quantify various array-level tradeoffs using full array SPICE circuit simulations based on layout-extracted parasitic netlists. This is then used to design the entire SOT-MRAM system along with a memory controller. Based on place and route (PnR), we evaluate the system-level PPA for various memory capacities, demonstrating bit densities up to 14.8 Mb/mm2 and read bandwidths up to 2.98 GB/s. Our results show that increasing the memory size from 1 to 16 Mb results in a performance degradation of ~33%–38% due to the impact of interconnect delay. As the results show that the performance of SOT-MRAM is limited by the interconnect delay, it is critical to co-optimize the device and interconnect technology to make SOT-MRAM a viable option at the advanced technology nodes. In addition, material discovery for field-free perpendicular magnetization switching in SOT devices based on out-of-plane spin torque is necessary to achieve SRAM-level write energies.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"139-147"},"PeriodicalIF":2.7,"publicationDate":"2025-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11202876","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145405389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0