电阻式内存计算架构的能耗与精度权衡

IF 2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Saion K. Roy;Naresh R. Shanbhag
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引用次数: 0

摘要

电阻式内存计算(IMC)架构由于计算精度低,目前在能效和计算密度方面都落后于 SRAM IMC 和数字加速器。本文提出使用信号噪声加失真比 (SNDR) 来量化 IMC 的计算精度,并确定影响精度的器件、电路和架构参数。我们进一步分析了磁阻式随机存取存储器 (MRAM-)、电阻式随机存取存储器 (ReRAM-) 和基于铁电场效应晶体管 (FeFET) 的 IMC 的 SNDR 基本限制,并采用了参数变化和噪声模型,这些模型与最近在 22 纳米工艺中基于 MRAM 的 IMC 原型的测量结果进行了验证。我们发现,在高输出信号幅度下,可实现的最大 SNDR 受限于前模数转换器 (ADC) 阵列的非理想性,如电导变化 (CV)、寄生电阻和电流镜失配 (MM),而 ADC 热噪声 (AT) 则限制了小信号幅度下的 SNDR。此外,对于大点积(DP)尺寸($N > 50$),FeFET 可实现的最大 SNDR 最高,其次是 ReRAM,再次是 MRAM。最后,电导对比度(${g_ {\text {ON}} }/ {g_ {\text {OFF}} }$)的增加只会提高最大可实现 SNDR,直到达到约 12 的值。ReRAM 和 FeFET 在实现高 SNDR 的同时,还具有较高的能效,因为它们的低电导值导致了较低的电流和由导线寄生导致的较低噪声。在所有情况下,在所有三种器件类型、DP 尺寸、ADC 精度和电导对比中,我们发现可实现的最大 SNDR 在 18-22 dB 之间,勉强达到实现接近等效定点数字架构推理精度所需的最低值。最后,我们展示了基于 ReRAM 的架构在 SNDR 为 22 dB 时映射 ResNet-20 (CIFAR-10) 所达到的 84.5% 的网络级精度,而基于 MRAM 和 FeFET 的架构无法实现这一精度。这一结果清楚地表明,需要采用其他方法(如基于算法和学习的方法)来提高电阻式 IMC 架构的推理精度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures
Resistive in-memory computing (IMC) architectures currently lag behind SRAM IMCs and digital accelerators in both energy efficiency and compute density due to their low compute accuracy. This article proposes the use of signal-to-noise-plus-distortion ratio (SNDR) to quantify the compute accuracy of IMCs and identify the device, circuit, and architectural parameters that affect it. We further analyze the fundamental limits on the SNDR of magnetoresistive random access memory (MRAM-), resistive random access memory (ReRAM-), and ferroelectric field effect transistor (FeFET)-based IMCs employing parameter variation and noise models that were validated against measured results from a recent MRAM-based IMC prototype in a 22 nm process. At high-output signal magnitude, we can find that the maximum achievable SNDR is limited by the pre-analog-to-digital-converter (ADC) array nonidealities, such as the conductance variations (CVs), parasitic resistances, and current mirror mismatch (MM), whereas the ADC thermal (AT) noise limits the SNDR at small signal magnitudes. Furthermore, for large dot-product (DP) dimensions ( $N > 50$ ), the maximum achievable SNDR is highest for FeFET, followed by ReRAM and then MRAM. Finally, the increase in conductance contrast ( ${g_ {\text {ON}} }/ {g_ {\text {OFF}} }$ ) enhances the maximum achievable SNDR only until it reaches a value of approximately 12. ReRAMs and FeFETs demonstrate high energy efficiencies while achieving high SNDR, as their low conductance values lead to lower currents and lower noise due to wire parasitics. In all cases, across all three device types, DP dimension, ADC precision, and conductance contrast, the maximum achievable SNDR is found to be in the range of 18–22 dB, barely meeting the minimum needed for achieving an inference accuracy close to an equivalent fixed-point digital architecture. Finally, we demonstrate a network-level accuracy of 84.5% when mapping an ResNet-20 (CIFAR-10) by ReRAM-based architecture at a SNDR of 22 dB, in which MRAM- and FeFET-based architectures cannot realize. This result clearly implies the need for other approaches, e.g., algorithmic- and learning-based methods, to improve the inference accuracy of resistive IMC architectures.
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来源期刊
CiteScore
5.00
自引率
4.20%
发文量
11
审稿时长
13 weeks
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