IEEE Journal on Exploratory Solid-State Computational Devices and Circuits最新文献

An Investigation of Minimum Supply Voltage of 5-nm SRAM From 300 K Down to 10 K 5nm SRAM最小供电电压从300k降至10k的研究

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2025-04-11 DOI: 10.1109/JXCDC.2025.3560215

Hafeez Raza;Shivendra Singh Parihar;Yogesh Singh Chauhan;Hussam Amrouch;Avinash Lahgere

{"title":"An Investigation of Minimum Supply Voltage of 5-nm SRAM From 300 K Down to 10 K","authors":"Hafeez Raza;Shivendra Singh Parihar;Yogesh Singh Chauhan;Hussam Amrouch;Avinash Lahgere","doi":"10.1109/JXCDC.2025.3560215","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3560215","url":null,"abstract":"In this article, we present a comprehensive study of the impact of cryogenic temperatures on the minimum operating voltage (<inline-formula> <tex-math>$V_{min }$ </tex-math></inline-formula>) of 5-nm Fin Field-Effect Transistors (FinFETs)-based Static Random Access Memory (SRAM) cells. To perform the SRAM <inline-formula> <tex-math>$V_{min }$ </tex-math></inline-formula> evaluation, we have measured the FinFETs fabricated using a commercial 5-nm technology down to 10 K. Next, we calibrate a cryogenic-aware BSIM-CMG FinFET compact model, which we use with our SRAM evaluation framework. For a comprehensive study, we evaluate three industry-standard SRAM cell types: 1) high-density cell (HDC); 2) low-voltage cell (LVC); and 3) high-performance cell (HPC). We analyze the impact of the threshold voltage (<inline-formula> <tex-math>$V_{text {TH}}$ </tex-math></inline-formula>) and gate length (<inline-formula> <tex-math>$L_{G}$ </tex-math></inline-formula>)-only variations on the SRAM noise resilience. At cryogenic temperature, minimum read voltage (<inline-formula> <tex-math>$V_{min ,R}$ </tex-math></inline-formula>) =0.15 V (62% decrease from room temperature) and minimum write voltage (<inline-formula> <tex-math>$V_{min ,W}$ </tex-math></inline-formula>) =0.45 V are achieved without read-/write-assist circuits. We also highlight that the LVC provides the best tradeoff for <inline-formula> <tex-math>$V_{min }$ </tex-math></inline-formula> between read and write operations for low-power cryogenic applications.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"42-50"},"PeriodicalIF":2.0,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10963695","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143925318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Cryogenic Hyperdimensional In-Memory Computing Using Ferroelectric TCAM 基于铁电TCAM的低温超维内存计算

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2025-03-04 DOI: 10.1109/JXCDC.2025.3547797

Shivendra Singh Parihar;Shubham Kumar;Swetaki Chatterjee;Girish Pahwa;Yogesh Singh Chauhan;Hussam Amrouch

{"title":"Cryogenic Hyperdimensional In-Memory Computing Using Ferroelectric TCAM","authors":"Shivendra Singh Parihar;Shubham Kumar;Swetaki Chatterjee;Girish Pahwa;Yogesh Singh Chauhan;Hussam Amrouch","doi":"10.1109/JXCDC.2025.3547797","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3547797","url":null,"abstract":"Cryogenic operations of electronics present a significant step forward to achieve huge demand of in-memory computing (IMC) for high-performance computing, quantum computing, and military applications. Ferroelectric (FE) is a promising candidate to develop the complementary metal oxide semiconductor (CMOS)-compatible nonvolatile memories. Hence, in this work, we investigate the effectiveness of IMC using emerging FE technology at the 5-nm technology node. To achieve that, we begin by characterizing commercial 5-nm fin field-effect transistors (FinFETs) from room temperature (300 K) down to cryogenic temperature (10 K). Then, we carefully calibrate the first industry-standard cryogenic-aware compact model [Berkeley Short-channel IGFET Model-Common Multi-Gate (BSIM-CMG)] to accurately reproduce the measurements. Afterward, we use the Preisach-model-based approach to incorporate the impact of FE within the BSIM-CMG model framework using the measurements from FE capacitor to realize ferroelectric fin field-effect transistors (Fe-FinFETs) operating from 300 down to 10 K. Then, as proof of concept, we focus on <inline-formula> <tex-math>$1times 8$ </tex-math></inline-formula> ternary content addressable memory (TCAM) array that is used to perform language classification and voice recognition using brain-inspired hyperdimensional IMC. Our comprehensive analysis spans from investigating the delay, power, and energy efficiency of TCAM-based IMC all the way up to calculating error probabilities in which we compare the figure of merits obtained from the emerging Fe-FinFET against classical FinFET-based IMC. We reveal that cryogenic temperatures lead to the worst performance in Fe-FinFET-based TCAM. Hence, we have also proposed solutions to improve the cryogenic performance of Fe-FinFET-based TCAM.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"34-41"},"PeriodicalIF":2.0,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10909519","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143777945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Device Nonideality-Aware Compute-in-Memory Array Architecting: Direct Voltage Sensing, I–V Symmetric Bitcell, and Padding Array 器件非理想性感知内存中计算阵列架构：直接电压传感、I-V对称位元和填充阵列

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2025-02-05 DOI: 10.1109/JXCDC.2025.3539470

Jianzi Jin;Shifan Gao;Cimang Lu;Xiang Qiu;Yi Zhao

{"title":"Device Nonideality-Aware Compute-in-Memory Array Architecting: Direct Voltage Sensing, I–V Symmetric Bitcell, and Padding Array","authors":"Jianzi Jin;Shifan Gao;Cimang Lu;Xiang Qiu;Yi Zhao","doi":"10.1109/JXCDC.2025.3539470","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3539470","url":null,"abstract":"A voltage sensing compute-in-memory (CIM) architecture has been designed to improve the analog computing accuracy, and a chip on 90-nm flash platform has been successfully fabricated, with the bidirectional operation enabled by the symmetric bitcell structure. By padding the weight sum to a global value for all bit lines (BLs), the costly multiplication postprocessing can be efficiently performed with the analog operation inside the array. The BL-differential voltage output scheme has two unique invariances. First, the so-called scaling invariance allows the weight matrix to be scaled to the full range for every BL. Second, the shifting invariance allows the weight to be tuned to a larger conductance with a better I–V linearity. Combined with the distributed padding, input voltage loss can also be reduced by suppressing the IR drop. The above schemes can significantly improve the linearity and reduce the relative weight error by >50%, as confirmed in applications from MNIST to face recognition, making it a promising solution for advanced artificial intelligence (AI) and memory computing applications.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"19-24"},"PeriodicalIF":2.0,"publicationDate":"2025-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10876176","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143553318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Binarized Neural-Network Parallel-Processing Accelerator Macro Designed for an Energy Efficiency Higher Than 100 TOPS/W 二值化神经网络并行处理加速器宏设计的能源效率高于100 TOPS/W

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2025-02-04 DOI: 10.1109/JXCDC.2025.3538702

Yusaku Shiotsu;Satoshi Sugahara

{"title":"Binarized Neural-Network Parallel-Processing Accelerator Macro Designed for an Energy Efficiency Higher Than 100 TOPS/W","authors":"Yusaku Shiotsu;Satoshi Sugahara","doi":"10.1109/JXCDC.2025.3538702","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3538702","url":null,"abstract":"A binarized neural-network (BNN) accelerator macro is developed based on a processing-in-memory (PIM) architecture having the ability of eight-parallel multiply-accumulate (MAC) processing. The parallel-processing PIM macro, referred to as a PPIM macro, is designed to perform the parallel processing with no use of multiport SRAM cells and to achieve the energy minimum point (EMP) operation for inference. The proposed memory array in the PPIM macro is configured with single-port Schmitt-trigger-type cells just by adding multiple bit lines with spatial address mapping modulation, resulting in a highly area-efficient cell array. The EMP operation of the developed PPIM macro can maximize the energy efficiency. As a result, an energy efficiency higher than 100 tera-operations-per-second per Watt (TOPS/W) can be achieved at around the EMP voltage. The EMP operation is also beneficial for enhancing the processing performance [measured in units of tera-operations per second (TOPS)] of the macro. The performance of fully connected-layer (FCL) networks configured with a multiple of the PPIM macro is also demonstrated.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"25-33"},"PeriodicalIF":2.0,"publicationDate":"2025-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10870055","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143602032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Co-Optimization of Power Delivery Network Design for 3-D Heterogeneous Integration of RRAM-Based Compute In-Memory Accelerators 基于rram的内存计算加速器三维异构集成的输电网络协同优化设计

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2025-01-27 DOI: 10.1109/JXCDC.2025.3534560

Madison Manley;James Read;Ankit Kaul;Shimeng Yu;Muhannad Bakir

{"title":"Co-Optimization of Power Delivery Network Design for 3-D Heterogeneous Integration of RRAM-Based Compute In-Memory Accelerators","authors":"Madison Manley;James Read;Ankit Kaul;Shimeng Yu;Muhannad Bakir","doi":"10.1109/JXCDC.2025.3534560","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3534560","url":null,"abstract":"Three-dimensional heterogeneous integration (3D-HI) offers promising solutions for incorporating substantial embedded memory into cutting-edge analog compute-in-memory (CIM) AI accelerators, addressing the need for on-chip acceleration of large AI models. However, this approach faces challenges with power supply noise (PSN) margins due to <inline-formula> <tex-math>$V_{text {DD}}$ </tex-math></inline-formula> scaling and increased power delivery network (PDN) impedance. This study demonstrates the necessity and benefits of 3D-HI for large-scale CIM accelerators, where 2-D implementations would exceed manufacturing reticle limits. Our 3-D designs achieve 39% higher energy efficiency, <inline-formula> <tex-math>$8times $ </tex-math></inline-formula> higher operation density, and improved throughput through shorter vertical interconnects. We quantify steady-state IR-drop impacts in 3D-HI CIM architectures using a framework that combines PDN modeling, 3D-HI power, performance, area estimation, and behavioral modeling. We demonstrate that a drop in supply voltage to CIM arrays increases sensitivity to process, voltage, and temperature (PVT) noise. Using our framework, we model IR-drop and simulate its impact on the accuracy of ResNet-50 and ResNet-152 when classifying images from the ImageNet 1k dataset in the presence of injected PVT noise. We analyze the impact of through-silicon via (TSV) design and placement to optimize the IR-drop and classification accuracy. For ResNet architectures in 3-D integration, we demonstrate that peripheral TSV placement provides an optimal balance between interconnect complexity and performance, achieving IR-drop below 10% of <inline-formula> <tex-math>$V_{text {DD}}$ </tex-math></inline-formula> while maintaining high classification accuracy.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"10-18"},"PeriodicalIF":2.0,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10854426","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143379553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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2024 Index IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Vol. 10 探索固态计算器件和电路的IEEE杂志第10卷

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2025-01-17 DOI: 10.1109/JXCDC.2025.3531616

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits publication information 探索性固态计算器件和电路IEEE杂志出版信息

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2025-01-16 DOI: 10.1109/JXCDC.2024.3499815

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INFORMATION FOR AUTHORS 作者信息

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2025-01-16 DOI: 10.1109/JXCDC.2024.3499819

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MESO-CMOS Hybrid Circuits With Time-Multiplexing Technique for Energy and Area-Efficient Computing in Memory 基于时间复用技术的MESO-CMOS混合电路在内存中的能量和面积高效计算

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2025-01-16 DOI: 10.1109/JXCDC.2025.3530906

Tzuping Huang;Linran Zhao;Yiming Han;Hai Li;Ian A. Young;Yaoyao Jia

{"title":"MESO-CMOS Hybrid Circuits With Time-Multiplexing Technique for Energy and Area-Efficient Computing in Memory","authors":"Tzuping Huang;Linran Zhao;Yiming Han;Hai Li;Ian A. Young;Yaoyao Jia","doi":"10.1109/JXCDC.2025.3530906","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3530906","url":null,"abstract":"The magnetoelectric spin orbit (MESO), one of the emerging spin devices, represents a promising alternative to complementary metal-oxide–semiconductor (CMOS) technology. MESO provides dual functionality: each device can perform logic operations while acting as a nonvolatile memory device. MESO also offers advantages, such as an ultralow supply voltage of 100 mV and the potential to vertically integrate with CMOS, which promises significant energy and area efficiency. These features support MESO’s suitability for improving the energy efficiency and area efficiency of computing-in-memory (CIM) circuits. To harness the advantages of MESO in large-scale complex circuit systems, this article presents the development of a MESO-based standard cell library. This library is critical to realize automated design, as it allows the implementation of all the basic CMOS functions with MESO, thereby enabling MESO-CMOS hybrid design in large-scale complex circuits. This article also introduces a highly area-efficient time-multiplexing technique to optimize the complex function inside CIM. Specifically, the multiplier and multiply-and-accumulate (MAC) circuits using the MESO-CMOS hybrid time-multiplexing technique reduce the area by 85% and 81%, respectively, compared to CMOS implementations.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"1-9"},"PeriodicalIF":2.0,"publicationDate":"2025-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10843777","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143379466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Special Topic on 3-D Logic and Memory for Energy Efficient Computing 面向节能计算的三维逻辑和存储器专题

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2025-01-07 DOI: 10.1109/JXCDC.2024.3518312

editorial

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