IEEE Journal on Exploratory Solid-State Computational Devices and Circuits最新文献

Special Topic on Modeling and Simulation of Emerging Materials, Devices, and Circuits for Energy-Efficient Computing 能源效率计算之新兴材料、装置与电路之建模与仿真专题

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-03-04 DOI: 10.1109/JXCDC.2026.3662448

Sumeet Gupta

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2025 Journal on Exploratory Solid-State Computational Devices and Circuits Vol. 11 探索性固态计算器件和电路杂志第11卷

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-15 DOI: 10.1109/JXCDC.2026.3654321

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Information for Authors 作者信息

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-09 DOI: 10.1109/JXCDC.2025.3632955

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Design and Analysis of a Three-Stream STT-MTJ TRNG With XOR and Majority Voter Logic as Postprocessing Architectures 以异或和多数选民逻辑作为后处理架构的三流STT-MTJ TRNG设计与分析

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-03-06 DOI: 10.1109/JXCDC.2026.3671608

M. Satwik Rai;Akshaja Kanugovi;Vinod Kumar Joshi

{"title":"Design and Analysis of a Three-Stream STT-MTJ TRNG With XOR and Majority Voter Logic as Postprocessing Architectures","authors":"M. Satwik Rai;Akshaja Kanugovi;Vinod Kumar Joshi","doi":"10.1109/JXCDC.2026.3671608","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3671608","url":null,"abstract":"True random number generators (TRNGs) are critical for hardware security, providing unpredictable entropy for cryptographic applications. Spin-transfer torque magnetic tunnel junction (STT-MTJ) devices offer a promising entropy source due to their low-power consumption, nonvolatility, and stochastic switching behavior. This work presents an MTJ-based TRNG that produces three independent bit streams. Two postprocessing architectures are investigated: (a) a three-input majority voter and (b) a two-input two-stage <sc>XOR</small> logic. Both schemes are evaluated in terms of entropy enhancement, bias reduction, and hardware efficiency. Simulation results demonstrate that the XOR-based design achieves superior statistical uniformity, while the majority voter provides improved fault tolerance. Both postprocessing approaches, exhibit similar energy consumption <inline-formula> <tex-math>$approx 13.4$ </tex-math></inline-formula> pJ/bit while achieving an identical throughput of 25 Mb/s. Randomness quality was validated using the National Institute of Standards and Technology (NIST) SP 800-22 test suite, and comparative analysis highlights the tradeoff between entropy maximization and reliability. The study provides design insights for secure and energy-efficient TRNG implementations in post-CMOS hardware platforms.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"36-44"},"PeriodicalIF":2.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11422881","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147606330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Characterization and Modeling of Multilevel Analog ReRAM Synapses in the Sky130 Process Sky130过程中多电平模拟ReRAM突触的表征和建模

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-03-04 DOI: 10.1109/JXCDC.2026.3670667

Irem Didin;Carl Brando;Ching-Yi Lin;Sahil Shah

{"title":"Characterization and Modeling of Multilevel Analog ReRAM Synapses in the Sky130 Process","authors":"Irem Didin;Carl Brando;Ching-Yi Lin;Sahil Shah","doi":"10.1109/JXCDC.2026.3670667","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3670667","url":null,"abstract":"Nonvolatile memory devices play a key role in enabling energy-efficient computing. Among them, analog nonvolatile memories such as resistive random access memory (ReRAM) offer high density and low power compared to conventional digital memories. However, their analog nature introduces device-level variability that impacts computational accuracy. This work presents the characterization and compact modeling of ReRAM devices fabricated in the SkyWater 130-nm CMOS process. A two-transistor–one-ReRAM (2T–1R) structure is used to isolate individual cells and mitigate sneak-path currents. Each cell occupies <inline-formula> <tex-math>$4.32~mu mathrm {m}^{2}$ </tex-math></inline-formula>, primarily determined by the access transistor sized for microampere-level currents. Statistical measurements are performed across multiple chips to quantify device-to-device variability and conductance distribution. Furthermore, a Verilog-A compact model is developed and calibrated to measured data, capturing nonlinear <inline-formula> <tex-math>$I$ </tex-math></inline-formula>–<inline-formula> <tex-math>$V$ </tex-math></inline-formula> behavior and variability for accurate circuit-level simulation. The resulting model enables reliable co-design of analog and neuromorphic systems that exploit ReRAM-based compute-in-memory (CIM) capabilities.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"27-35"},"PeriodicalIF":2.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11421367","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147557388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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OISMA: On-the-Fly In-Memory Stochastic Multiplication Architecture for Approximate Matrix Multiplication 近似矩阵乘法的动态内存随机乘法体系结构

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-04-02 DOI: 10.1109/JXCDC.2026.3680281

Shady Agwa;Yihan Pan;Georgios Papandroulidakis;Themis Prodromakis

{"title":"OISMA: On-the-Fly In-Memory Stochastic Multiplication Architecture for Approximate Matrix Multiplication","authors":"Shady Agwa;Yihan Pan;Georgios Papandroulidakis;Themis Prodromakis","doi":"10.1109/JXCDC.2026.3680281","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3680281","url":null,"abstract":"Artificial intelligence (AI) models are currently driven by a significant upscaling of their complexity, with massive matrix-multiplication workloads representing the major computational bottleneck. In-memory computing (IMC) architectures are proposed to avoid the von Neumann bottleneck. However, both digital/binary-based and analog IMC architectures suffer from various limitations, which significantly degrade the performance and energy efficiency gains. This work proposes OISMA, an energy-efficient IMC architecture that utilizes the computational simplicity of a quasi-stochastic computing (SC) domain (bent-pyramid (BP) system) while keeping the same efficiency, scalability, and productivity of digital memories. OISMA converts normal memory read operations into in situ stochastic multiplication operations with a negligible cost. An accumulation periphery then accumulates the output multiplication bitstreams, achieving the matrix multiplication (MatMul) functionality. A 4-kB 1T1R OISMA array was implemented using a commercial 180-nm technology node and in-house resistive random-access memory (RRAM) technology. At 50 MHz, it achieves 0.789 TOPS/W and 3.98 GOPS/mm2 for energy and area efficiency, respectively, occupying an effective computing area of 0.804241 mm2. Scaling OISMA to 22-nm technology shows a significant improvement of two orders of magnitude in energy efficiency and one order of magnitude in area efficiency, compared to dense MatMul IMC architectures.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"56-64"},"PeriodicalIF":2.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11473289","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147665518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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A Novel VGSOT-pMTJ Write Circuit for Hybrid CMOS/MTJ CIM Architecture 一种新型CMOS/MTJ - CIM混合结构的VGSOT-pMTJ写电路

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-04-01 DOI: 10.1109/JXCDC.2026.3679830

Prashanth Barla;Ramya Moodakare

{"title":"A Novel VGSOT-pMTJ Write Circuit for Hybrid CMOS/MTJ CIM Architecture","authors":"Prashanth Barla;Ramya Moodakare","doi":"10.1109/JXCDC.2026.3679830","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3679830","url":null,"abstract":"Hybrid computation-in-memory (CIM) architecture has emerged as the most promising alternative to overcome the drawbacks of the conventional CMOS-only devices used in the conventional von-Neumann architecture. In the hybrid CIM architecture, a pair of perpendicular magnetic tunnel junctions (pMTJs) is used to store one bit of information. Though there are different methods by which one can store information in the pMTJ pair, the voltage gate spin–orbit torque (VGSOT) is the most prominent due to its advantages over the rest. In this work, a novel write circuit has been proposed that stores information into the pMTJ pair using the VGSOT mechanism. The proposed circuit was implemented and evaluated using the Cadence Virtuoso tool. Comparison of the novel write circuit with the existing one reveals a significant improvement of 77.56% in energy efficiency, 87.01% reduction in delay, 97.09% in energy delay product (EDP), and a 50% decrease in transistor count. Monte Carlo simulations further show that the proposed write circuit achieves lower energy consumption in its worst case than the best-case energy consumption of the existing design, highlighting its robustness and energy efficiency.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"65-69"},"PeriodicalIF":2.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11460228","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147696180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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LUT-Based Convolutional Tsetlin Machine Accelerator With Dynamic Clause Scaling for Resources-Constrained FPGAs 基于lut的动态子句缩放卷积Tsetlin机器加速器在资源受限fpga中的应用

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-03-23 DOI: 10.1109/JXCDC.2026.3676833

Rashed Al Amin;Roman Obermaisser

{"title":"LUT-Based Convolutional Tsetlin Machine Accelerator With Dynamic Clause Scaling for Resources-Constrained FPGAs","authors":"Rashed Al Amin;Roman Obermaisser","doi":"10.1109/JXCDC.2026.3676833","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3676833","url":null,"abstract":"The rapid growth of machine learning (ML) workloads, particularly in computer vision applications, has significantly increased computational and energy demands in modern electronic systems, motivating the use of hardware accelerators to offload processing from general-purpose processors. Despite advances in computationally efficient ML models, achieving energy-efficient inference on resource-constrained edge devices remains a significant challenge. The Tsetlin machine (TM) has emerged as an attractive alternative for image classification due to its high throughput and inherently energy-efficient learning paradigm. However, existing TM-based hardware accelerators struggle to balance classification accuracy and energy efficiency, limiting their practical deployment at the edge. This article presents a resource- and energy-efficient convolutional TM (CTM) accelerator with dynamic clause scaling, optimized explicitly for edge field-programmable gate array (FPGA) platforms. The proposed architecture employs LUT-based pipelining and targeted resource-optimization techniques to minimize FPGA resource utilization while maintaining high-energy efficiency and performance. The accelerator is implemented on a Xilinx Zybo-Z20 FPGA and evaluated using the MNIST, Fashion-MNIST (FMNIST), and Kuzushiji-MNIST (KMNIST) datasets, achieving classification accuracies of 97.78%, 85.53%, and 88.54%, respectively, with an energy consumption of up to <inline-formula> <tex-math>$0.3~mu $ </tex-math></inline-formula>J per image classification. Compared with state-of-the-art CTM accelerators, the proposed design achieves up to <inline-formula> <tex-math>$40times $ </tex-math></inline-formula> improvements in resource and energy efficiency, demonstrating its suitability for real-time image and pattern classification on edge FPGA-based systems.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"45-55"},"PeriodicalIF":2.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11454583","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147606329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Antiferromagnetic Programmable Neuron: Structure, Training, and Pattern Recognition Applications 反铁磁可编程神经元：结构、训练和模式识别应用

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2025-11-17 DOI: 10.1109/JXCDC.2025.3633490

I. Sotnyk;O. Prokopenko

{"title":"Antiferromagnetic Programmable Neuron: Structure, Training, and Pattern Recognition Applications","authors":"I. Sotnyk;O. Prokopenko","doi":"10.1109/JXCDC.2025.3633490","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3633490","url":null,"abstract":"Artificial neurons based on antiferromagnetic (AFM) spin Hall oscillators (SHOs) are promising elements for creating ultrafast, energy-efficient neuromorphic computing systems. These structures can generate picosecond spikes in response to dc and ac electric currents, thereby mimicking the reaction of biological neurons to an external stimulus. However, conventional AFM neurons have only one input, which significantly limits their applications. In this article, we propose an approach to the implementation of a programmable artificial neuron (P-neuron) based on conventional AFM neurons in the form of a simple, two-layer neural network. Each neuron in the first layer has an independent input, and all of their outputs are connected to a single main neuron in the second layer. This configuration allows the sensitivity of system to individual input signals to be changed independently and in real time by regulating the dc current applied to the first-layer neurons, which makes it possible to program the entire P-neuron structure. In addition, the P-neuron demonstrates the ability for controlled training. We demonstrate that a multi-input P-neuron can successfully classify small images (<inline-formula> <tex-math>$5times 5$ </tex-math></inline-formula> pixels) of English alphabet symbols. Recognition is based on analyzing the time characteristics of the output neuron signal and comparing them with reference samples. We believe that the obtained results are important for the development and optimization of ultrafast neural network based on AFM nanostructures and AFM spintronic devices capable of generating and processing (sub)terahertz-frequency signals.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"9-17"},"PeriodicalIF":2.7,"publicationDate":"2025-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11250656","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145969438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Integrated Spatiotemporal Multiscale- Multiphysics-Uncertainty Simulation for Controlling Variability in RRAM Devices 集成时空多尺度-多物理场-不确定性模拟用于控制RRAM器件的可变性

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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2025-11-14 DOI: 10.1109/JXCDC.2025.3633067

Ziyan Liao;Zhiheng Huang;Min Xiao;Yuezhong Meng;Hui Yan;Yang Liu

{"title":"Integrated Spatiotemporal Multiscale- Multiphysics-Uncertainty Simulation for Controlling Variability in RRAM Devices","authors":"Ziyan Liao;Zhiheng Huang;Min Xiao;Yuezhong Meng;Hui Yan;Yang Liu","doi":"10.1109/JXCDC.2025.3633067","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3633067","url":null,"abstract":"Resistive random access memory (RRAM) is a leading candidate for next-generation nonvolatile memory and neuromorphic computing. However, its performance is limited by inherent switching variability and uncertainties in spatiotemporal multiscale materials and processes. This study integrates multiphysics and multiscale modeling with uncertainty quantification (UQ) to systematically address these limitations and reduce uncertainties. UQ identifies critical inputs that govern key performance metrics, including the<sc>ON</small>/<sc>OFF</small> ratio, forming voltage, and power consumption, reducing their statistical distributions with the probabilities of reliability analysis over 92%. The phase field model (PFM) captures the morphological evolution of conductive filament (CF) and, by incorporating a second-order time derivative for ion diffusion, reveals the impact of morphological fluctuations governing RRAM behavior. Drift diffusion simulations further demonstrate that bilayer structures confine CF fractures to the HfO2 layer through interfacial constraints. This modeling framework provides a systematic approach to mitigate variability and improve the design and reliability of RRAM devices.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"1-8"},"PeriodicalIF":2.7,"publicationDate":"2025-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11248831","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145969437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0