IEEE Journal on Exploratory Solid-State Computational Devices and Circuits最新文献

Special Topic on Modeling and Simulation of Emerging Materials, Devices, and Circuits for Energy-Efficient Computing 能源效率计算之新兴材料、装置与电路之建模与仿真专题

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-03-04 DOI: 10.1109/JXCDC.2026.3662448

Sumeet Gupta

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2025 Journal on Exploratory Solid-State Computational Devices and Circuits Vol. 11 探索性固态计算器件和电路杂志第11卷

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-15 DOI: 10.1109/JXCDC.2026.3654321

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Information for Authors 作者信息

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-09 DOI: 10.1109/JXCDC.2025.3632955

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OISMA: On-the-Fly In-Memory Stochastic Multiplication Architecture for Approximate Matrix Multiplication 近似矩阵乘法的动态内存随机乘法体系结构

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-04-02 DOI: 10.1109/JXCDC.2026.3680281

Shady Agwa;Yihan Pan;Georgios Papandroulidakis;Themis Prodromakis

{"title":"OISMA: On-the-Fly In-Memory Stochastic Multiplication Architecture for Approximate Matrix Multiplication","authors":"Shady Agwa;Yihan Pan;Georgios Papandroulidakis;Themis Prodromakis","doi":"10.1109/JXCDC.2026.3680281","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3680281","url":null,"abstract":"Artificial intelligence (AI) models are currently driven by a significant upscaling of their complexity, with massive matrix-multiplication workloads representing the major computational bottleneck. In-memory computing (IMC) architectures are proposed to avoid the von Neumann bottleneck. However, both digital/binary-based and analog IMC architectures suffer from various limitations, which significantly degrade the performance and energy efficiency gains. This work proposes OISMA, an energy-efficient IMC architecture that utilizes the computational simplicity of a quasi-stochastic computing (SC) domain (bent-pyramid (BP) system) while keeping the same efficiency, scalability, and productivity of digital memories. OISMA converts normal memory read operations into in situ stochastic multiplication operations with a negligible cost. An accumulation periphery then accumulates the output multiplication bitstreams, achieving the matrix multiplication (MatMul) functionality. A 4-kB 1T1R OISMA array was implemented using a commercial 180-nm technology node and in-house resistive random-access memory (RRAM) technology. At 50 MHz, it achieves 0.789 TOPS/W and 3.98 GOPS/mm2 for energy and area efficiency, respectively, occupying an effective computing area of 0.804241 mm2. Scaling OISMA to 22-nm technology shows a significant improvement of two orders of magnitude in energy efficiency and one order of magnitude in area efficiency, compared to dense MatMul IMC architectures.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"56-64"},"PeriodicalIF":2.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11473289","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147665518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Design and Analysis of a Three-Stream STT-MTJ TRNG With XOR and Majority Voter Logic as Postprocessing Architectures 以异或和多数选民逻辑作为后处理架构的三流STT-MTJ TRNG设计与分析

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-03-06 DOI: 10.1109/JXCDC.2026.3671608

M. Satwik Rai;Akshaja Kanugovi;Vinod Kumar Joshi

{"title":"Design and Analysis of a Three-Stream STT-MTJ TRNG With XOR and Majority Voter Logic as Postprocessing Architectures","authors":"M. Satwik Rai;Akshaja Kanugovi;Vinod Kumar Joshi","doi":"10.1109/JXCDC.2026.3671608","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3671608","url":null,"abstract":"True random number generators (TRNGs) are critical for hardware security, providing unpredictable entropy for cryptographic applications. Spin-transfer torque magnetic tunnel junction (STT-MTJ) devices offer a promising entropy source due to their low-power consumption, nonvolatility, and stochastic switching behavior. This work presents an MTJ-based TRNG that produces three independent bit streams. Two postprocessing architectures are investigated: (a) a three-input majority voter and (b) a two-input two-stage <sc>XOR</small> logic. Both schemes are evaluated in terms of entropy enhancement, bias reduction, and hardware efficiency. Simulation results demonstrate that the XOR-based design achieves superior statistical uniformity, while the majority voter provides improved fault tolerance. Both postprocessing approaches, exhibit similar energy consumption <inline-formula> <tex-math>$approx 13.4$ </tex-math></inline-formula> pJ/bit while achieving an identical throughput of 25 Mb/s. Randomness quality was validated using the National Institute of Standards and Technology (NIST) SP 800-22 test suite, and comparative analysis highlights the tradeoff between entropy maximization and reliability. The study provides design insights for secure and energy-efficient TRNG implementations in post-CMOS hardware platforms.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"36-44"},"PeriodicalIF":2.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11422881","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147606330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Characterization and Modeling of Multilevel Analog ReRAM Synapses in the Sky130 Process Sky130过程中多电平模拟ReRAM突触的表征和建模

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-03-04 DOI: 10.1109/JXCDC.2026.3670667

Irem Didin;Carl Brando;Ching-Yi Lin;Sahil Shah

{"title":"Characterization and Modeling of Multilevel Analog ReRAM Synapses in the Sky130 Process","authors":"Irem Didin;Carl Brando;Ching-Yi Lin;Sahil Shah","doi":"10.1109/JXCDC.2026.3670667","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3670667","url":null,"abstract":"Nonvolatile memory devices play a key role in enabling energy-efficient computing. Among them, analog nonvolatile memories such as resistive random access memory (ReRAM) offer high density and low power compared to conventional digital memories. However, their analog nature introduces device-level variability that impacts computational accuracy. This work presents the characterization and compact modeling of ReRAM devices fabricated in the SkyWater 130-nm CMOS process. A two-transistor–one-ReRAM (2T–1R) structure is used to isolate individual cells and mitigate sneak-path currents. Each cell occupies <inline-formula> <tex-math>$4.32~mu mathrm {m}^{2}$ </tex-math></inline-formula>, primarily determined by the access transistor sized for microampere-level currents. Statistical measurements are performed across multiple chips to quantify device-to-device variability and conductance distribution. Furthermore, a Verilog-A compact model is developed and calibrated to measured data, capturing nonlinear <inline-formula> <tex-math>$I$ </tex-math></inline-formula>–<inline-formula> <tex-math>$V$ </tex-math></inline-formula> behavior and variability for accurate circuit-level simulation. The resulting model enables reliable co-design of analog and neuromorphic systems that exploit ReRAM-based compute-in-memory (CIM) capabilities.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"27-35"},"PeriodicalIF":2.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11421367","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147557388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Topology-Aware Layout Design for Area-Decoupled Transistor Sizing in Multitier CFET SRAM 多层CFET SRAM中面积去耦晶体管尺寸的拓扑感知布局设计

IF 3.1

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-07-01 DOI: 10.1109/JXCDC.2026.3709007

Yutian Zhang;Jiaquan Fang;Khawar Sarfraz;Mansun Chan

{"title":"Topology-Aware Layout Design for Area-Decoupled Transistor Sizing in Multitier CFET SRAM","authors":"Yutian Zhang;Jiaquan Fang;Khawar Sarfraz;Mansun Chan","doi":"10.1109/JXCDC.2026.3709007","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3709007","url":null,"abstract":"This work shows that a multitier complementary FET (CFET) static random access memory (SRAM) can decouple the area term from PPA-oriented transistor sizing. A topology-aware layout design is used to construct orthogonal and point-symmetric multitier CFET SRAM cells under 1-nm-class design rules, enabling high-density (HD), high-performance (HP), and high-current (HC) sizing at an identical cell boundary. Three-dimensional field-solver extraction identifies a topology-dependent bitline (BL) and wordline (WL) time-constant optimum: the three-tier mapping minimizes the BL time constant while avoiding the superlinear supply-rail resistance penalty observed at four tiers. Back-annotated <inline-formula> <tex-math>$128times 128$ </tex-math></inline-formula> array SPICE simulations show that a three-tier HC 6T SRAM achieves <inline-formula> <tex-math>$7.4times $ </tex-math></inline-formula> read-delay and <inline-formula> <tex-math>$2.6times $ </tex-math></inline-formula> write-delay improvements over the two-tier HD baseline while retaining a 25.0% smaller array-compatible footprint. The same results show that 6T sizing freedom cannot remove the intrinsic read–write stability tradeoff of the shared access path. Extending the layout approach to 8T SRAM adds an independently sized read port, making the read static noise margin (RSNM) equal to the hold static noise margin (HSNM) across the evaluated tier configurations and reducing the read delay by 40%–42% without additional XY-area cost. These results establish multitier CFET SRAM as a layout regime in which area-decoupled transistor sizing becomes a practical circuit-design variable.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"159-166"},"PeriodicalIF":3.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11592380","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148486211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Sensing- and Periphery-Aware Modeling of a Hybrid MTJ–CMOS Nonvolatile 1-bit Sign-Weight Memory Subsystem for Energy-Constrained Edge Inference 基于能量约束边缘推断的混合MTJ-CMOS非易失性1位符号权重存储子系统的感知和外围感知建模

IF 3.1

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-08-24 DOI: 10.1109/JXCDC.2026.3726699

Byeong-Gwon Kim;Byeong-Kwon Ju;Ki-Young Lee

{"title":"Sensing- and Periphery-Aware Modeling of a Hybrid MTJ–CMOS Nonvolatile 1-bit Sign-Weight Memory Subsystem for Energy-Constrained Edge Inference","authors":"Byeong-Gwon Kim;Byeong-Kwon Ju;Ki-Young Lee","doi":"10.1109/JXCDC.2026.3726699","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3726699","url":null,"abstract":"The spin-transfer-torque magnetic random access memory (STT-MRAM) is attractive for nonvolatile 1-bit sign-weight storage, but a favorable cell or local-read metric does not establish subsystem efficiency. We analyze a hybrid magnetic tunnel junction (MTJ)–complementary metal–oxide–semiconductor (CMOS) memory subsystem, in which MTJs store static signs while sensing, reference generation, sign staging, scale handling, and accumulation remain in CMOS; the subsystem is storage plus readout, not compute-in-memory. We first correct the energy boundary: a reported 28-nm capacitor-powered sensing/read-path value of 1 pJ/bit at 1.2 V is treated as an inclusive local-read quantity, giving a first-order <inline-formula> <tex-math>$V^{2}$ </tex-math></inline-formula> projection of 0.293 pJ/bit at 0.65 V, not an array-only measurement. We then derive a conditional criterion for support-circuit energy to exceed the array-cell term. For declared low, central, and high structural assumptions, dominance requires an assumed local-support fraction <inline-formula> <tex-math>$q$ </tex-math></inline-formula> above 0.430, 0.388, and 0.308, respectively; a decoupled <inline-formula> <tex-math>$3times 3$ </tex-math></inline-formula> sensitivity spans 44.3%–57.3%, with the central case at 49.1%. A public SKY130 reconstruction is retained only as a qualitative topology stress test, not an advanced-node projection. A controlled Bonsai-1.7B sign-inversion experiment conditionally evaluates perplexity sensitivity without mapping imposed faults to MTJ bit-error rate. No fabricated array, extracted layout, measured MTJ energy, physical yield, or token-level speedup is claimed. The result is an assumption-transparent bound showing when read support becomes co-dominant and what evidence is still required for a physical subsystem claim.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"192-198"},"PeriodicalIF":3.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11664398","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148924079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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The Impact of Magnetic Field on Defective FDSOI and FinFET Devices 磁场对缺陷FDSOI和FinFET器件的影响

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-04-23 DOI: 10.1109/JXCDC.2026.3686904

Munazza Sayed;Hussam Amrouch

{"title":"The Impact of Magnetic Field on Defective FDSOI and FinFET Devices","authors":"Munazza Sayed;Hussam Amrouch","doi":"10.1109/JXCDC.2026.3686904","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3686904","url":null,"abstract":"This article explores the efficacy of a unique defect detection mechanism for the FinFET and FDSOI transistors: magnetomodulation of drain current. Using multiphysics technology CAD (TCAD), we model the impact of static and transient magnetic fields on drain current in the following defect-free and defective devices: 1) FDSOI with interface trap defects and 1) FinFET with gate stack defects. To optimize the magnetic field sensitivity of FDSOI, we evaluate the effects of voltage bias and key device parameters, such as gate oxide thickness, buried oxide thickness, and temperature. We investigate the FDSOI under two different magnetic fields, 2 and 10 T, with the resulting drain current decreasing in the linear region by approximately 1.0% and 19.9%, respectively. Furthermore, aging analysis accounting for bias temperature instability (BTI) at 2 T shows minimal drain current change in a ten-year-aged device—0.05% for NBTI and 0.07% for PBTI. This underscores the limited current magnetomodulation in FDSOI. For the FinFET gate-defect analysis, Ion/Ioff reduces by 0.04% for the same defective device in the presence and absence of a magnetic field. The analysis concludes that the resulting differences in magnetomodulated drain current at 2 T are insufficient to serve as a reliable diagnostic marker for the devices under consideration and the specific bias conditions. Nonetheless, this work introduces and rigorously investigates a novel diagnostic strategy, highlighting possible avenues for further exploration in advanced semiconductor technologies at higher magnetic fields.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"113-119"},"PeriodicalIF":2.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11494007","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148171999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Open DRAM Model—Part I: Cross-Layer Device, Array, and Circuit Analysis With BL-to-BL Coupling Mitigation for 4F2 VCT DRAM 开放式DRAM模型-第一部分：4F2 VCT DRAM的跨层器件、阵列和电路分析与bl - bl耦合缓解

IF 3.1

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-06-17 DOI: 10.1109/JXCDC.2026.3704358

Kiseok Lee;Seongkwang Lim;Suman Datta;Shimeng Yu

{"title":"Open DRAM Model—Part I: Cross-Layer Device, Array, and Circuit Analysis With BL-to-BL Coupling Mitigation for 4F2 VCT DRAM","authors":"Kiseok Lee;Seongkwang Lim;Suman Datta;Shimeng Yu","doi":"10.1109/JXCDC.2026.3704358","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3704358","url":null,"abstract":"Dynamic random access memory (DRAM) scaling toward 4F2 vertical channel transistors (VCTs) fundamentally reshapes device, array, and circuit-level design tradeoffs. However, the lack of an open-source DRAM device model that is calibrated with recent industry trends prohibits broader innovations in the research community. In this work, we present an “Open DRAM Model” and showcase its application in cross-layer modeling and analysis for 4F2 VCT, spanning access-device electrostatics, array parasitics, sense margin, disturbance mechanisms, and peripheral integration under a CMOS-bonded-array (CBA) architecture. Based on publicly available disclosures, we construct TCAD-calibrated compact models and array-level frameworks. Our analysis reveals that while 4F2 VCTs benefit from reduced bitline (BL) capacitance (CBL) and increased initial sense margin, severe BL-to-BL direct coupling emerges as a first-order bottleneck and causes sensing failures. To address this, we evaluate two complementary mitigation strategies: 1) a cell-level partial (half) BL shielding scheme and 2) a circuit-level folded-like twisted BL sense amplifier (BLSA) topology. The proposed half-shield scheme achieves a balanced tradeoff between coupling suppression and CBL inflation, recovering positive sense margin under worst case (<inline-formula> <tex-math>$6.28sigma $ </tex-math></inline-formula>) variability. Furthermore, the folded-like twisted BLSA enables robust sensing even without cell-level shielding, while simultaneously improving sensing latency through effective differential coupling cancellation (nominal random cycle time: baseline D1b 21.5 ns, VCT 12.0 ns). By providing quantitative design guidelines, this work establishes a practical foundation for future 4F2 VCT DRAM technology pathfinding and system-technology co-optimization.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"135-143"},"PeriodicalIF":3.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11569031","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148484922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0