Mohammad Khairul Bashar;T. H. Pantha;Z. Li;M. Farasat;S. Datta;V. Narayanan;S. Dutta;N. Shukla
{"title":"FIMA: A Scalable Ferroelectric Compute-in-Memory Annealer for Accelerating Boolean Satisfiability","authors":"Mohammad Khairul Bashar;T. H. Pantha;Z. Li;M. Farasat;S. Datta;V. Narayanan;S. Dutta;N. Shukla","doi":"10.1109/JXCDC.2025.3603942","DOIUrl":null,"url":null,"abstract":"In-memory compute kernels present a promising approach for addressing data-centric workloads. However, their scalability—particularly for computationally intensive tasks solving combinatorial optimization problems such as Boolean satisfiability (SAT), which are inherently difficult to decompose—remains a significant challenge. In this work, we propose a ferroelectric nonvolatile memory (NVM)-based compute-in-memory annealer for solving the Boolean MaxSAT problem. We experimentally demonstrate the computational functionality of the NVM array using a compact <inline-formula> <tex-math>$20 \\times 10$ </tex-math></inline-formula> HZO-/IWO-based ferroelectric field-effect-transistor (FeFET) array. More importantly, through experimentally calibrated simulations, we demonstrate that our solution is compatible with a modular memory architecture, allowing the problem sizes to exceed the capacity of a single memory array. Our approach not only addresses the size limitations imposed by the read margin (RM) of individual arrays but also opens new avenues for integrating such accelerators as back-end solutions in advanced computing platforms.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"81-89"},"PeriodicalIF":2.7000,"publicationDate":"2025-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11143213","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/11143213/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
In-memory compute kernels present a promising approach for addressing data-centric workloads. However, their scalability—particularly for computationally intensive tasks solving combinatorial optimization problems such as Boolean satisfiability (SAT), which are inherently difficult to decompose—remains a significant challenge. In this work, we propose a ferroelectric nonvolatile memory (NVM)-based compute-in-memory annealer for solving the Boolean MaxSAT problem. We experimentally demonstrate the computational functionality of the NVM array using a compact $20 \times 10$ HZO-/IWO-based ferroelectric field-effect-transistor (FeFET) array. More importantly, through experimentally calibrated simulations, we demonstrate that our solution is compatible with a modular memory architecture, allowing the problem sizes to exceed the capacity of a single memory array. Our approach not only addresses the size limitations imposed by the read margin (RM) of individual arrays but also opens new avenues for integrating such accelerators as back-end solutions in advanced computing platforms.