IEEE Journal on Exploratory Solid-State Computational Devices and Circuits最新文献

{"title":"Self-Heating and Parasitic Effects in Multi-Tier CFET Design","authors":"Sufia Shahin;Mahdi Benkhelifa;Yogesh Singh Chauhan;Hussam Amrouch","doi":"10.1109/JXCDC.2026.3704373","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3704373","url":null,"abstract":"In this article, we study the impact of self-heating effects (SHEs) and middle of line (MOL) and back-end of line (BEOL) induced parasitics on multi-tier CFET design, where multiple nanosheet devices are vertically stacked. We analyze and compare the four-tier complementary FET (CFET) design with the conventional two-tier CFET, using TCAD models calibrated to experimental measurements. In addition, TCAD simulations are used to model and analyze SHE-induced heat distribution and temperature profiles and to extract the detailed parasitic RC network from 3-D models of CMOS inverters designed with full MOL and BEOL interconnects. At the device level, the maximum temperature rise (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>TMAX) caused by SHE in nFET and pFET devices of the two-tier CFET architecture is 62 and 74 K, respectively. Due to the increased distance from the substrate heat sink, the upper-tier nFET and pFET devices in the four-tier design show higher <inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>TMAX of 83.5 and 98.5 K and more heat trapping in the stacked layers. Furthermore, in the four-tier CFET-based CMOS inverters, the BEOL-induced parasitic RCs are, respectively, 10 and 6.5 times higher in the top-tier than in the two-tier CFET-based inverters. In the bottom tier, the corresponding parasitic RC elements are 6.26 and 2 times higher, respectively, than in the two-tier inverters. Finally, compared to the four-tier design without parasitics, the propagation delay of the top and bottom tier inverters increases by 10% and 8.2%, respectively, due to the interconnect parasitic RCs. For the conventional two-tier inverter, the corresponding degradation of delay with parasitic RCs is 37.25%.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"153-158"},"PeriodicalIF":3.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11569014","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148486260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Compact XOR Gate Implemented With a Single Straintronic Magnetic Tunnel Junction","authors":"Supriyo Bandyopadhyay","doi":"10.1109/JXCDC.2026.3719208","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3719208","url":null,"abstract":"The <sc>xor</small> Boolean logic gate is widely used in many applications such as encryption (<sc>xor</small> ciphers), binary addition (half- and full-adders), error detection (parity bits), etc., but is challenging to construct because of its demanding conditional dynamics. It typically requires multiple logic switches or other types of gates, which results in a large gate footprint and low logic density. Here, we present the design of an <sc>xor</small> gate with a single straintronic magnetic tunnel junction (MTJ) which reduces the footprint dramatically. Such a gate is nonvolatile and hence suitable for non-von-Neumann architectures, processor-in-memory, etc. The switching time of the gate is ~200 ps and the energy dissipation per gate operation is ~225 aJ. Cascading of successive stages is accomplished via a CMOS device which plays no role in the gate dynamics but is needed for gain to provide logic level restoration, fan-out, and isolation between input and output. This one MTJ–one CMOS design has an energy dissipation that is an order of magnitude smaller than what has been reported for traditional all-transistor <sc>xor</small> designs.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"185-191"},"PeriodicalIF":3.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11638071","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148749208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel VGSOT-pMTJ Write Circuit for Hybrid CMOS/MTJ CIM Architecture","authors":"Prashanth Barla;Ramya Moodakare","doi":"10.1109/JXCDC.2026.3679830","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3679830","url":null,"abstract":"Hybrid computation-in-memory (CIM) architecture has emerged as the most promising alternative to overcome the drawbacks of the conventional CMOS-only devices used in the conventional von-Neumann architecture. In the hybrid CIM architecture, a pair of perpendicular magnetic tunnel junctions (pMTJs) is used to store one bit of information. Though there are different methods by which one can store information in the pMTJ pair, the voltage gate spin–orbit torque (VGSOT) is the most prominent due to its advantages over the rest. In this work, a novel write circuit has been proposed that stores information into the pMTJ pair using the VGSOT mechanism. The proposed circuit was implemented and evaluated using the Cadence Virtuoso tool. Comparison of the novel write circuit with the existing one reveals a significant improvement of 77.56% in energy efficiency, 87.01% reduction in delay, 97.09% in energy delay product (EDP), and a 50% decrease in transistor count. Monte Carlo simulations further show that the proposed write circuit achieves lower energy consumption in its worst case than the best-case energy consumption of the existing design, highlighting its robustness and energy efficiency.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"65-69"},"PeriodicalIF":2.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11460228","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147696180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Current-Mode Nondestructive Circuit Readout Scheme for High-Density 3-D Ferroelectric Memory","authors":"Chaohan Wang;Wagdy Hussein;Yang Xiang;Shankha Mukherjee;Ismail Cevik;Fernando García-Redondo;Annachiara Spagnolo;Hyungrock Oh;Marie Garcia Bardon;Nick van Helleputte;Julien Ryckaert;Geert Hellings;Dwaipayan Biswas;Jan van Houdt","doi":"10.1109/JXCDC.2026.3727137","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3727137","url":null,"abstract":"The AI era is demanding ever-increasing memory capacity and bandwidth, where 3-D-stacked ferroelectric memory (FeRAM) utilizing nondestructive readout (NDRO) ferroelectric capacitors (FeCAPs) stand as a promising candidate. This work addresses NDRO sensing signal challenges in deeply scaled 3-D FeRAMs using a current-mode sensing scheme, co-designed with the device architecture to overcome signal degradation due to capacitive charge sharing. By exploring gm cell design and time-differential bipolar readout, we demonstrate the feasibility of 3-D stacking up to 128 FeCAPs while maintaining sub-<inline-formula> <tex-math>$mu s$ </tex-math></inline-formula> access, transcending the conventional charge-sharing-defined stacking limit of 64 and achieving an effective bit density of <inline-formula> <tex-math>${sim}200~text{Mb/mm}^{2}$ </tex-math></inline-formula>. Using a two-stage Miller-compensated high-GBW operational transconductance amplifier (OTA) implementation, we additionally underscore the robustness of our sensing scheme against variability in CMOS circuits, but also in bit-cell FeCAPs, such as FeCAP area variation (~80%), memory window fluctuation (~15 aF), and work function asymmetry (~200 mV). The proposed architecture further provides a flexible design tradeoff between read speed and energy consumption, where a single-stage low-power OTA design allows read energy scaling down to ~10 pJ/bit at <inline-formula> <tex-math>$mu s$ </tex-math></inline-formula>-level access time. The FeCAP model is calibrated to experimental data, ensuring realistic simulation fidelity. These results offer instrumental insights into the design-technology co-optimization (DTCO) of 3-D FeRAM-based storage-class memories (SCMs).","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"199-204"},"PeriodicalIF":3.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11666836","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148985803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Open DRAM Model—Part II: Enabling Processing-in-Memory in 3-D DRAM","authors":"Kiseok Lee;Seongkwang Lim;Suman Datta;Shimeng Yu","doi":"10.1109/JXCDC.2026.3704508","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3704508","url":null,"abstract":"Processing-in-memory (PIM) by implementing Boolean logic functions in dynamic random access memory (DRAM) has been proposed to alleviate the memory wall problem in data-intensive computing. However, quantitatively evaluating DRAM-based logic operations across different DRAM architectures remains challenging due to the lack of publicly available DRAM cell and peripheral transistor models that accurately capture their behavior. In this work, we present an “Open DRAM Model” that enables comprehensive circuit-level analysis of DRAM operations across multiple architectures, including conventional 6F2 BCAT, scaled 4F2 VCT, and monolithically stacked 3-D DRAM. The model incorporates both cell characteristics and peripheral sensing circuits, enabling a realistic evaluation of the sense margin and timing behavior. Using this open model framework, we analyze triple-row activation (TRA), a widely studied primitive for implementing majority-based logic in DRAM. Our analysis shows that although TRA inherently reduces the sense margin due to multirow charge sharing, the absence of retention-induced charge loss allows reliable sensing even when tail variations are considered. The results show that TRA remains practically feasible across the evaluated DRAM architectures. We further investigate the practicality of the dual-contact cells (DCCs) scheme for implementing NOT operations. Our analysis reveals that DCC introduces significant layout and routing constraints, making its integration difficult in highly scaled DRAM arrays and vertically stacked 3-D DRAM. To address this limitation, we propose a bitline sense amplifier (BLSA)-level <sc>not</small> operation that performs inversion directly within the BLSA, eliminating the need for DCC in the cell array. SPICE simulations across 6F2, 4F2, and 3-D DRAM confirm the correct functionality of the proposed scheme.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"144-152"},"PeriodicalIF":3.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11569022","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148485799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"DTCO of NOR-Type IGZO FeFETs for 3-D Heterogeneous AI Memories: A Read-Centric Perspective","authors":"Yang Xiang;Zhuo Chen;Nicolò Ronchi;Arvind Sharma;Fernando García-Redondo;Subhali Subhechha;Attilio Belmonte;Maarten Rosmeulen;Gouri Sankar Kar;Dwaipayan Biswas;Jan Van Houdt","doi":"10.1109/JXCDC.2026.3740054","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3740054","url":null,"abstract":"InGaZnO (IGZO)-channel FeFETs have attracted notable interest thanks to recent advances in endurance, opening up their application space for read-dominated AI memory tiers. This work evaluates the viability of NOR-type IGZO FeFETs for 3-D heterogeneous AI memories from a read-centric design-technology co-optimization (DTCO) perspective, spanning on-chip back-end-of-line (BEOL) random-access memories (RAMs) and hybrid-bonded memory chiplets, and off-chip, monolithically integrated 3-D FeNOR storage-class memories (SCMs). For on-chip BEOL RAMs and memory chiplets, we demonstrate the cross-node bitcell footprint scalability of IGZO FeFETs capable of delivering down to 10-Å static random-access memory (SRAM)-equivalent bitcell area (<inline-formula> <tex-math>$sim 0.016~mu $ </tex-math></inline-formula>m2) with 7-nm ground rules while maintaining a sub-5-ns random access latency—despite their writability challenges. We further identify the sensing margin (SM) penalty in NOR FeFET arrays arising from sneak current associated with the negative program-state <inline-formula> <tex-math>$V_{t}$ </tex-math></inline-formula>, which requires positive-<inline-formula> <tex-math>$V_{t}$ </tex-math></inline-formula> engineering in order to eliminate the unwanted negative voltage read inhibition—for example, by ferroelectric layer thinning. Last but not least, we elucidate the read margin implications on 3-D FeNOR for SCMs, with the 3-D stacking density limited by additional sneak current from neighbor channel shunting.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"249-255"},"PeriodicalIF":3.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11719656","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149188223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Information for Authors","authors":"","doi":"10.1109/JXCDC.2026.3662082","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3662082","url":null,"abstract":"","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"C3-C3"},"PeriodicalIF":3.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11563570","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148433214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Probabilistic Computing With Neuromorphic Elements","authors":"Zonglong Li;Laurie E. Calvet","doi":"10.1109/JXCDC.2026.3712198","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3712198","url":null,"abstract":"This article presents a compact and low-power approach to probabilistic inference based on time-domain analog computation. The proposed system implements a Bayesian classifier using neuromorphic circuit elements simulated in a 130-nm CMOS technology. Probabilities are encoded in the duty cycle of deterministic spiking signals generated by neuron circuits, while likelihood functions are directly embedded in the parameters of synapse-like analog circuits. Posterior probabilities are obtained through temporal interactions between these signals using simple circuit primitives, notably either an analog coincidence detection or a Muller C-element. The final decision is determined using a time-to-first-spike (TTFS) encoding scheme. In contrast to prior hardware implementations that rely on stochastic sampling, memory-based representations, or explicit evaluation of probabilistic graphs, the proposed approach performs inference through the continuous-time dynamics of a statically configured analog circuit. This avoids random-number generation for probability-stream generation, explicit memory access, and analog-to-digital (ADC) conversion during inference. The approach is validated through circuit-level simulations on a breast cancer classification task, achieving accuracies of 73%–90%, comparable to software implementations, while operating in the <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>W power range. These results demonstrate a compact and energy-efficient solution for low-dimensional probabilistic inference, particularly suited for near-sensor and edge computing applications.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"167-175"},"PeriodicalIF":3.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11603382","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148628141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SEAL: Multitenant Security-Aware Layer Mapping for Heterogeneous 3-D CiM Accelerators","authors":"Pragya Sharma;Sriniketh Purisai Ramanujam;Ashish Reddy Bommana;Hossein Pourmehrani;Naghmeh Karimi;Farshad Firouzi;Krishnendu Chakrabarty","doi":"10.1109/JXCDC.2026.3734047","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3734047","url":null,"abstract":"Heterogeneous 3-D compute-in-memory (CiM) architectures have emerged as an efficient acceleration paradigm for deep neural network (DNN) inference by leveraging the complementary characteristics of diverse memory technologies enabled through 3-D integration. Prior work has focused on architectural efficiency and workload-mapping optimization, leaving the security implications of heterogeneous CiM systems largely unexplored. This gap becomes critical in multitenant deployments, where the shared power delivery network (PDN) exposes the system to a ground-bounce-driven fault-injection attack: a malicious co-tenant drives switching-intensive activity that shifts the victim chiplet’s ground reference, corrupting memory reads during inference and degrading output quality. We propose SEAL, a security-aware layer-mapping framework that co-optimizes power, performance, area (PPA), and fault vulnerability across the layer-to-tier search space. SEAL combines per-layer criticality with device-level fault sensitivity to route vulnerability-critical layers to fault-resilient (device, tier) combinations, and we report the power and area of every mapping we present. We evaluate SEAL on ResNet-18 (CIFAR-10) and Qwen2.5-3B (WikiText-2) under attacker-induced ground bounce. SEAL reduces fault vulnerability by up to <inline-formula> <tex-math>$3.9times $ </tex-math></inline-formula> on ResNet-18 and <inline-formula> <tex-math>$7.8times $ </tex-math></inline-formula> on Qwen2.5-3B over a security-blind mapping baseline on compositions where both methods find usable mappings. On ReRAM-heavy compositions, SEAL places every high-criticality layer on a low-vulnerability tier and drives fault vulnerability to the characterization floor, an operating point the security-blind baseline does not reach. Accuracy stays within 0.06 pp of the fault-free baseline on ResNet-18 and perplexity within 0.06 of the fault-free baseline on Qwen2.5-3B. SEAL further finds usable mappings on three compositions (two on ResNet-18 and one on Qwen2.5-3B) where the security-blind baseline finds none.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"205-213"},"PeriodicalIF":3.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11692886","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149133695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits publication information","authors":"","doi":"10.1109/JXCDC.2026.3662078","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3662078","url":null,"abstract":"","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"C2-C2"},"PeriodicalIF":3.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11563568","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148433304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}