IEEE Journal on Exploratory Solid-State Computational Devices and Circuits最新文献

{"title":"Energy-Accuracy Trade-Offs for Resistive In-Memory Computing Architectures","authors":"Saion K. Roy;Naresh R. Shanbhag","doi":"10.1109/JXCDC.2024.3381888","DOIUrl":"https://doi.org/10.1109/JXCDC.2024.3381888","url":null,"abstract":"Resistive in-memory computing (IMC) architectures currently lag behind SRAM IMCs and digital accelerators in both energy efficiency and compute density due to their low compute accuracy. This article proposes the use of signal-to-noise-plus-distortion ratio (SNDR) to quantify the compute accuracy of IMCs and identify the device, circuit, and architectural parameters that affect it. We further analyze the fundamental limits on the SNDR of magnetoresistive random access memory (MRAM-), resistive random access memory (ReRAM-), and ferroelectric field effect transistor (FeFET)-based IMCs employing parameter variation and noise models that were validated against measured results from a recent MRAM-based IMC prototype in a 22 nm process. At high-output signal magnitude, we can find that the maximum achievable SNDR is limited by the pre-analog-to-digital-converter (ADC) array nonidealities, such as the conductance variations (CVs), parasitic resistances, and current mirror mismatch (MM), whereas the ADC thermal (AT) noise limits the SNDR at small signal magnitudes. Furthermore, for large dot-product (DP) dimensions (\u0000<inline-formula> <tex-math>$N &gt; 50$ </tex-math></inline-formula>\u0000), the maximum achievable SNDR is highest for FeFET, followed by ReRAM and then MRAM. Finally, the increase in conductance contrast (\u0000<inline-formula> <tex-math>${g_ {text {ON}} }/ {g_ {text {OFF}} }$ </tex-math></inline-formula>\u0000) enhances the maximum achievable SNDR only until it reaches a value of approximately 12. ReRAMs and FeFETs demonstrate high energy efficiencies while achieving high SNDR, as their low conductance values lead to lower currents and lower noise due to wire parasitics. In all cases, across all three device types, DP dimension, ADC precision, and conductance contrast, the maximum achievable SNDR is found to be in the range of 18–22 dB, barely meeting the minimum needed for achieving an inference accuracy close to an equivalent fixed-point digital architecture. Finally, we demonstrate a network-level accuracy of 84.5% when mapping an ResNet-20 (CIFAR-10) by ReRAM-based architecture at a SNDR of 22 dB, in which MRAM- and FeFET-based architectures cannot realize. This result clearly implies the need for other approaches, e.g., algorithmic- and learning-based methods, to improve the inference accuracy of resistive IMC architectures.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2024-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10478888","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140544290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of Technology Scaling and Back-End-of-the-Line Technology Solutions on Magnetic Random-Access Memories","authors":"Piyush Kumar;Da Eun Shim;Siri Narla;Azad Naeemi","doi":"10.1109/JXCDC.2024.3357625","DOIUrl":"https://doi.org/10.1109/JXCDC.2024.3357625","url":null,"abstract":"While magnetic random-access memories (MRAMs) are promising because of their nonvolatility, relatively fast speeds, and high endurance, there are major challenges in adopting them for the advanced technology nodes. One of the major challenges in scaling MRAM devices is caused by the ever-increasing resistances of interconnects. In this article, we first study the impact of shrunk interconnect dimensions on MRAM performance at various technology nodes. Then, we investigate the impact of various potential back-end-of-the-line (BEOL) technology solutions at the 7 nm node. Based on interconnect resistance values from technology computer-aided design (TCAD) simulations and MRAM device characteristics from experimentally validated/calibrated physical models, we quantify the potential array-level performance of MRAM using SPICE simulations. We project that some potential BEOL technology solutions can reduce the write energy by up to 34.6% with spin–orbit torque (SOT) MRAM and 29.0% with spin-transfer torque (STT) MRAM. We also observe up to 21.4% reduction in the read energy of the SOT-MRAM arrays.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2024-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10412202","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139732024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Source Design of Vertical III–V Nanowire Tunnel Field-Effect Transistors","authors":"Gautham Rangasamy;Zhongyunshen Zhu;Lars-Erik Wernersson","doi":"10.1109/JXCDC.2024.3355949","DOIUrl":"https://doi.org/10.1109/JXCDC.2024.3355949","url":null,"abstract":"We systematically fabricate devices and analyze data for vertical InAs/(In)GaAsSb nanowire tunnel field-effect transistors (TFETs), to study the influence of source dopant position and level on their device performance. The results show that delaying the introduction of dopants further in the GaAsSb source segments improved the transistor metrics (subthreshold swing (SS) and the on-current performance), due to the formation of a nid-InAsSb segment. The devices display a minimum SS of 26 mV/dec and on-current of \u0000<inline-formula> <tex-math>$10.2 ~mu text{A}/mu text{m}$ </tex-math></inline-formula>\u0000 at \u0000<inline-formula> <tex-math>$V_{text {DS}}$ </tex-math></inline-formula>\u0000 of 300 mV. The performance of devices were improved further by optimizing the doping levels which led to record subthermal current of \u0000<inline-formula> <tex-math>$1.2 ~mu text{A}/mu text{m}$ </tex-math></inline-formula>\u0000 and transconductance of \u0000<inline-formula> <tex-math>$205 ~mu text{S}/mu text{m}$ </tex-math></inline-formula>\u0000 at \u0000<inline-formula> <tex-math>$V_{text {DS}}$ </tex-math></inline-formula>\u0000 of 500 mV.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2024-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10409158","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139727453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits publication information","authors":"","doi":"10.1109/JXCDC.2023.3333712","DOIUrl":"https://doi.org/10.1109/JXCDC.2023.3333712","url":null,"abstract":"","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10416972","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139654258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits—Volume 9, No. 2","authors":"Azad Naeemi","doi":"10.1109/JXCDC.2023.3349088","DOIUrl":"https://doi.org/10.1109/JXCDC.2023.3349088","url":null,"abstract":"Welcome to the seventh volume, second semiannual issue of IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC), a multidisciplinary, open-access IEEE journal that is focused on publishing seminal research in the exploration of energy-efficient computing based on physics and materials to enable new devices, circuits, and architecture that will be of great interest to integrated circuit researchers and those working in the IT industry. The articles in the journal are selectively chosen to provide insight into the architectural, circuit, and device implications of emerging quantum nanoelectronic and nanomagnetic device technologies. The discovery of new materials, devices, and circuits for energy-efficient computational circuits will be needed to enable Moore’s law to continue for computing beyond the end of the roadmap for CMOS technologies, with significant improvement in energy efficiency and cost per function.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10406188","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139494229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Special Topic on Physics-Based Modeling and Simulation of Materials, Devices, and Circuits of Beyond-CMOS Logic and Memory Technologies for Energy-Efficient Computing","authors":"Sumeet Kumar Gupta","doi":"10.1109/JXCDC.2023.3340557","DOIUrl":"https://doi.org/10.1109/JXCDC.2023.3340557","url":null,"abstract":"Standard complementary metal–oxide–semiconductor (CMOS) technology and its advanced flavors in the form of FinFETs have propelled the electronic industry to its extraordinary success. While the CMOS technology may continue to deliver its remarkably powerful performance to next-generation computing platforms, it is quite clear that in the longer term, it has major challenges in scaling, suffers from power consumption and power density limitations, and may not be amenable to the new demands of the emerging applications. This will require beyond-CMOS technologies to step in and augment CMOS. Whether it is the design of energy-efficient scalable switches for logic design, or nonvolatile memory, or the integration of memory and logic functionalities for general-purpose computers and application-specific accelerators, the need for the application of quantum materials to realize these new microelectronic devices has surged.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10378858","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139081220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"2023 Index IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Vol. 9","authors":"","doi":"10.1109/JXCDC.2024.3361278","DOIUrl":"https://doi.org/10.1109/JXCDC.2024.3361278","url":null,"abstract":"","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10419070","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139676173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"INFORMATION FOR AUTHORS","authors":"","doi":"10.1109/JXCDC.2023.3340380","DOIUrl":"https://doi.org/10.1109/JXCDC.2023.3340380","url":null,"abstract":"","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10416945","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139654237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"INFORMATION FOR AUTHORS","authors":"","doi":"10.1109/JXCDC.2023.3333716","DOIUrl":"https://doi.org/10.1109/JXCDC.2023.3333716","url":null,"abstract":"","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10416971","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139654236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits publication information","authors":"","doi":"10.1109/JXCDC.2023.3340376","DOIUrl":"https://doi.org/10.1109/JXCDC.2023.3340376","url":null,"abstract":"","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10416963","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139654742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}