IEEE Journal on Exploratory Solid-State Computational Devices and Circuits最新文献

{"title":"Energy-Efficient Logic-in-Memory and Neuromorphic Computing in Raised Source and Drain MOSFETs","authors":"Md. Hasan Raza Ansari;Bashayr Alqahtani;Naveen Kumar;Vihar Georgiev;Nazek El-Atab","doi":"10.1109/JXCDC.2025.3630217","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3630217","url":null,"abstract":"This work highlights the potential application of raised source and drain (RSD) MOSFETs-based charge trapping memory (CTM) for next-generation computing applications. This simulation study presents a double-gate (DG)-RSD MOSFET technology with a short gate length (50 nm) to significantly improve the performance of logic-in-memory (LIM) and neuromorphic computing (NC) systems. By taking advantage of the superior electrostatic control and reduced parasitic resistance provided by RSD MOSFETs, this work aims to reduce energy consumption for LIM and NC applications. The CTM operation is based on the Fowler–Nordheim (FN) tunneling mechanism, performing 16 Boolean logic functions in two steps: program (PGM) and read operations, including <sc>or</small>, <sc>and</small>, <sc>nor</small>, <sc>nand</small>, <sc>xor</small>, and <sc>xnor</small>. Furthermore, the device shows synapse capability by mimicking long-term potentiation (LTP) and depression long-term depression (LTD) while achieving good linearity and symmetricity between the conductance values. The results reveal that energy consumption for LIM is ~21.4 and ~68.9 fJ for the NC application. This simulation result also demonstrates a high level of accuracy of 88.19%, with less than a 2.04% difference compared to software-based neural networks (90.23%). These multifunctional capabilities of DG-RSD-based CTM highlight the potential application for next-generation computing.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"197-204"},"PeriodicalIF":2.7,"publicationDate":"2025-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11232511","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145560776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Integrating Atomistic Insights With Circuit Simulations via Transformer-Driven Symbolic Regression","authors":"Md Rahatul Islam Udoy;Jack Hutchins;Shamiul Alam;Catherine Schuman;Ahmedullah Aziz","doi":"10.1109/JXCDC.2025.3624662","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3624662","url":null,"abstract":"This article introduces a framework that establishes a cohesive link between the first principles-based simulations and circuit-level analyses using a machine learning-based compact modeling platform. Starting with atomistic simulations, the framework examines the microscopic details of material behavior, forming the foundation for later stages. The generated datasets, with molecular insights, are processed using machine learning (ML) algorithms to identify complex patterns and relationships. As these machine-learning models develop, they become tools for predicting behaviors beyond the reach of conventional modeling and simulation methods. Applied to circuit simulation, the framework improves understanding of electrical interactions, enhancing accuracy and speeding up design automation. As a proof of concept, we perform first principles-based simulations of the graphene nanoribbon field effect transistor (GNRFET), an exploratory device, and create a symbolic-regression-based ML model that can readily be integrated into advanced circuit simulation. This framework presents a template offering a unified approach that synergizes the strengths of first principles-based simulations and circuit-level design tools.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"179-187"},"PeriodicalIF":2.7,"publicationDate":"2025-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11215792","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A SPICE-Compatible Compact Model of Ferroelectric Diode","authors":"Musaib Rafiq;Mohammad Sajid Nazir;Ateeb Naseer;Yogesh Singh Chauhan;Shubham Sahay","doi":"10.1109/JXCDC.2025.3624212","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3624212","url":null,"abstract":"In this work, for the first time, we present a SPICE-compatible compact model of ferroelectric (FE) diodes to enable their design exploration for diverse applications, including memory and unconventional computing paradigms. We propose modified Schottky barrier and hopping models for capturing the on- and off-mode operations of the FE diode, respectively, in conjunction with the multidomain Preisach model for incorporating the FE switching. Since the operating regime of the FE diode is determined by the polarization state and the sign of the applied voltage, directional dependence is also introduced in the proposed model to effectively capture the experimentally observed current–voltage characteristics. The proposed FE-diode model is validated by accurately reproducing two sets of asymmetric experimental current–voltage characteristics of BE/HZO/IGZO/TE FE diodes.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"166-170"},"PeriodicalIF":2.7,"publicationDate":"2025-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11214353","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of Aging, Self-Heating, and Parasitics Effects on NSFET and CFET","authors":"Swati Deshwal;Sufia Shahin;Anirban Kar;Yogesh S. Chauhan;Hussam Amrouch","doi":"10.1109/JXCDC.2025.3624653","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3624653","url":null,"abstract":"This work presents a comparative analysis of complementary field-effect transistor (CFET) and nanosheet FET (NSFET) architectures, with a focus on self-heating effects (SHEs), negative bias temperature instability (NBTI), hot carrier degradation (HCD), and the impact of back-end-of-line (BEOL) parasitics on standard cell performance. NBTI degradation is modeled using a framework combining reaction–diffusion (RD) and reaction–drift–diffusion (RDD) mechanisms in TCAD. BEOL parasitics are extracted using TCAD-generated structures. Both the CFET and NSFET exhibit similar degradation behavior under NBTI stress. However, CFETs show more pronounced degradation due to HCD, primarily driven by stronger SHE. Next, we simulate CFET- and NSFET-based 3-D inverters and SRAM structures in TCAD, with BEOL interconnects up to M3 level, to study the impact of parasitics on the circuit performance. Meanwhile, CFETs offer ~50% area savings at the standard cell level and lower parasitics, leading to a 42% improvement in inverter propagation delay. The SRAM cells based on CFETs are also evaluated and compared against NSFET in terms of area, noise margins, and performance. The CFET SRAM cell provides area gain along with faster and more stable write operations, providing a potential advantage in high-performance applications compared to NSFET.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"188-196"},"PeriodicalIF":2.7,"publicationDate":"2025-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11215725","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Quantum Field Theory Model for Spin-Based Devices Using 2-D van der Waals Materials","authors":"Axel I. Saenz Rodriguez;Oksana Ostroverkhova;Pallavi Dhagat","doi":"10.1109/JXCDC.2025.3624217","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3624217","url":null,"abstract":"We explore the effects of layered geometries of 2-D quantum spin systems as a method to tune and control material properties for spintronic devices. We analyze the dispersion relation of a 2-D quantum spin system with a shifted bilayer square lattice through the linear spin wave (LSW) approximation of quantum field theory (QFT). Inspired by recent interest in 2-D van der Waals (vdW) magnetic materials, we consider both short-range interactions given by nearest-neighbor intralayer ferromagnetic and interlayer antiferromagnetic spin-exchange interactions and long-range dipole–dipole interactions. This case, along with lattice shifts, has not been treated in the literature via LSW theory. Computations show the gap in the frequencies for the two lowest-energy magnon modes at zero wavenumber that depend on the horizontal and vertical layer shifts. The frequency gap is attributed to the long-range dipole interaction with the gap becoming more sensitive to the horizontal layer shifts for small layer separation. Our general framework is suitable for numerical computations of a wide collection of 2-D lattice models and presents an essential first step toward a comprehensive model that can incorporate quantum effects leading to quantifiable predictions of additional physical properties, for example, spin coherence length and damping, of interest for engineering of spintronic devices.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"171-178"},"PeriodicalIF":2.7,"publicationDate":"2025-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11214338","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comprehensive Device to System Co-Design for SOT-MRAM at the 7 nm Node","authors":"Piyush Kumar;Da Eun Shim;Azad Naeemi","doi":"10.1109/JXCDC.2025.3621279","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3621279","url":null,"abstract":"This work presents a comprehensive spin-orbit torque (SOT)-based magnetic random access memory (MRAM) design at the 7 nm technology node, spanning from device-level characteristics to system-level power performance area (PPA). At the device level, we show the tradeoffs among the write current, error rate, and time, based on mircomagnetic simulations. Based on ASAP7 PDK design rules, we create the bit-cell and peripheral layouts for SOT-MRAM and design the entire array. In addition, we quantify various array-level tradeoffs using full array SPICE circuit simulations based on layout-extracted parasitic netlists. This is then used to design the entire SOT-MRAM system along with a memory controller. Based on place and route (PnR), we evaluate the system-level PPA for various memory capacities, demonstrating bit densities up to 14.8 Mb/mm2 and read bandwidths up to 2.98 GB/s. Our results show that increasing the memory size from 1 to 16 Mb results in a performance degradation of ~33%–38% due to the impact of interconnect delay. As the results show that the performance of SOT-MRAM is limited by the interconnect delay, it is critical to co-optimize the device and interconnect technology to make SOT-MRAM a viable option at the advanced technology nodes. In addition, material discovery for field-free perpendicular magnetization switching in SOT devices based on out-of-plane spin torque is necessary to achieve SRAM-level write energies.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"139-147"},"PeriodicalIF":2.7,"publicationDate":"2025-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11202876","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145405389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"1.58-b FeFET-Based Ternary Neural Networks: Achieving Robust Compute-In-Memory With Weight-Input Transformations","authors":"Imtiaz Ahmed;Akul Malhotra;Revanth Koduru;Sumeet Kumar Gupta","doi":"10.1109/JXCDC.2025.3621160","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3621160","url":null,"abstract":"Ternary weight neural networks (TWNs), with weights quantized to three states (−1, 0, and 1), have emerged as promising solutions for resource-constrained edge artificial intelligence (AI) platforms due to their high energy efficiency with acceptable inference accuracy. Further energy savings can be achieved with TWN accelerators utilizing techniques such as compute-in-memory (CiM) and scalable technologies such as ferroelectric transistors (FeFETs). Although the standard 1T-FeFET CiM design offers high density with its compactness and multilevel storage, its CiM performance in deeply scaled technology is prone to hardware nonidealities. This requires design modifications such as 2T-FeFET bitcells, offering high CiM robustness due to their differential nature at the cost of area. In this work, we conduct a design space exploration of FeFET-based TWN-CiM solutions. By utilizing FeFETs storing 1 bit (two levels) and 1.58 (<inline-formula> <tex-math>$log _{2}3$ </tex-math></inline-formula>) bits (three levels), we design three flavors of ternary CiM arrays: 1) 1T design based on 1.58-b FeFET (1T); 2) 2T differential (2T-diff) design; and 3) 2T pull-up/pull-down (2T-PUPD) design. Additionally, to increase the computational robustness of the 1T design, we propose static-weight transformation (WT) and static-weight input transformation (WIT). We then comparatively evaluate the inference accuracy and energy–area tradeoffs of these designs. For this, we use phase-field models to capture the multidomain physics and a rigorous inference simulator accounting for hardware nonidealities. Our analysis for ResNet18 trained on the CIFAR100 dataset shows that 1.58-b 1T-bitcell with WT and WIT techniques yield significant improvement in inference accuracy (73.61%) compared to the standard 1T design (i.e., without WIT). This accuracy is comparable to the 2T-diff design (76.4%), with <inline-formula> <tex-math>$1.98times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$1.91times $ </tex-math></inline-formula> reduction in overall area and CiM energy, respectively.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"157-165"},"PeriodicalIF":2.7,"publicationDate":"2025-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11202915","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Understanding Reliability Trade-Offs in 1T-nC and 2T-nC FeRAM Designs","authors":"Sadik Yasir Tauki;Rudra Biswas;Rakesh Acharya;Jiahui Duan;Rajiv Joshi;Kai Ni;Vijaykrishnan Narayanan","doi":"10.1109/JXCDC.2025.3619908","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3619908","url":null,"abstract":"Ferroelectric random access memory (FeRAM) is a promising candidate for energy-efficient nonvolatile memory, particularly for logic-in-memory and compute-in-memory (CIM) applications. Among the available cell architectures, One-Transistor–n-Capacitor (1T-nC) and two-transistor–n-capacitor (2T-nC) FeRAMs each offer distinct trade-offs in density, scalability, and reliability. In this work, we present a comparative study of these two architectures under both dimensional scaling (<inline-formula> <tex-math>$XY$ </tex-math></inline-formula>/Z shrinkage) and vertical integration (increasing stacked capacitors per cell). Using technology computer-aided design (TCAD) and circuit-level simulations, we analyze how scaling impacts ferroelectric capacitance, parasitic coupling, and floating-node (FN) dynamics, which together dictate sense margin (SM) and read stability. A key mitigation strategy—floating unselected capacitors—is applied to both architectures, effectively decoupling the SM from the number of stacked capacitors and enabling tractable analysis across scaling regimes. Results show that 1T-nC suffers more from charge sharing with the bitline (BL), while 2T-nC benefits from transistor isolation and stronger low-voltage sensing at the cost of increased area. By systematically evaluating these behaviors across scaling directions, this work establishes the reliability trade-offs of 1T-nC and 2T-nC cells and provides design guidelines for high-density, vertically integrated FeRAM systems.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"148-156"},"PeriodicalIF":2.7,"publicationDate":"2025-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11197534","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Non-Volatile ReRAM-Based Compact Event-Triggered Counters","authors":"Moin Diwan;Shengchao Zhang;Zidu Li;Alex James;Bhaskar Choubey","doi":"10.1109/JXCDC.2025.3619415","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3619415","url":null,"abstract":"With an increasing number of transistors per circuit, the fabrication cost and the energy consumption of each integrated circuits increase exponentially, which drives the need to reduce the number of transistors. In this study, we explore a novel design for a 16-bit digital counter that utilizes a combination of complementary metal–oxide–semiconductor (CMOS) circuits and memristors (ReRAM), thereby reducing the number of transistors and finding applications in artificial intelligence (AI) circuits. Two types of a 16-bit digital counter have been designed, one of which is a classically designed D-flip-flop (DFF) using memristors as logic gates, followed by an improved design that significantly reduces the number of components. The results of the design and simulation of 16-bit digital counters are presented with an expected counter function. The simulation is based on experimentally measured parameters of memristors and a functional model. Furthermore, in-depth analyses with respect to practical memristor results are discussed, including variations in set/reset potential, endurance and retention characteristics, post-layout effects on the proposed circuit, and the associated power consumption.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"131-138"},"PeriodicalIF":2.7,"publicationDate":"2025-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11196921","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145352227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Benchmarking of FERAM-Based Memory System by Optimizing Ferroelectric Device Model","authors":"Mohammad Adnaan;Saeideh Alinezhad Chamazcoti;Emil Karimov;Marie Garcia Bardon;Francky Catthoor;Jan van Houdt;Azad Naeemi","doi":"10.1109/JXCDC.2025.3618883","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3618883","url":null,"abstract":"We present a framework for design technology co-optimization (DTCO) of the main memory system with one transistor-one capacitor (1T1C) ferroelectric random access memory (FERAM) as an alternative to dynamic random access memory (DRAM). We start with the ferroelectric capacitor device model and perform array-level memory circuit simulation. Then, we map the circuit-level metrics to system-level simulators to analyze the performance enhancement of using FERAM as a main memory. We demonstrate the performance boost and power savings that can be achieved at the system level by improving individual device characteristics and modifying circuit architecture. We have estimated that on average more than 14% improvement in instruction per cycle and 21% reduction in energy consumption can be achieved by substituting DRAM with FERAM equipped with a ferroelectric capacitor having an optimal polarization switching voltage of 1.5 V.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"99-106"},"PeriodicalIF":2.7,"publicationDate":"2025-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11195120","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145352266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}