IEEE Journal on Exploratory Solid-State Computational Devices and Circuits最新文献

{"title":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits publication information","authors":"","doi":"10.1109/JXCDC.2023.3333712","DOIUrl":"https://doi.org/10.1109/JXCDC.2023.3333712","url":null,"abstract":"","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"9 2","pages":"C2-C2"},"PeriodicalIF":2.4,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10416972","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139654258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Special Topic on Physics-Based Modeling and Simulation of Materials, Devices, and Circuits of Beyond-CMOS Logic and Memory Technologies for Energy-Efficient Computing","authors":"Sumeet Kumar Gupta","doi":"10.1109/JXCDC.2023.3340557","DOIUrl":"https://doi.org/10.1109/JXCDC.2023.3340557","url":null,"abstract":"Standard complementary metal–oxide–semiconductor (CMOS) technology and its advanced flavors in the form of FinFETs have propelled the electronic industry to its extraordinary success. While the CMOS technology may continue to deliver its remarkably powerful performance to next-generation computing platforms, it is quite clear that in the longer term, it has major challenges in scaling, suffers from power consumption and power density limitations, and may not be amenable to the new demands of the emerging applications. This will require beyond-CMOS technologies to step in and augment CMOS. Whether it is the design of energy-efficient scalable switches for logic design, or nonvolatile memory, or the integration of memory and logic functionalities for general-purpose computers and application-specific accelerators, the need for the application of quantum materials to realize these new microelectronic devices has surged.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"9 2","pages":"ii-iv"},"PeriodicalIF":2.4,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10378858","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139081220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"2023 Index IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Vol. 9","authors":"","doi":"10.1109/JXCDC.2024.3361278","DOIUrl":"https://doi.org/10.1109/JXCDC.2024.3361278","url":null,"abstract":"","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"9 2","pages":"185-190"},"PeriodicalIF":2.4,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10419070","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139676173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"INFORMATION FOR AUTHORS","authors":"","doi":"10.1109/JXCDC.2023.3340380","DOIUrl":"https://doi.org/10.1109/JXCDC.2023.3340380","url":null,"abstract":"","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"9 2","pages":"C3-C3"},"PeriodicalIF":2.4,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10416945","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139654237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"INFORMATION FOR AUTHORS","authors":"","doi":"10.1109/JXCDC.2023.3333716","DOIUrl":"https://doi.org/10.1109/JXCDC.2023.3333716","url":null,"abstract":"","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"9 2","pages":"C3-C3"},"PeriodicalIF":2.4,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10416971","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139654236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits publication information","authors":"","doi":"10.1109/JXCDC.2023.3340376","DOIUrl":"https://doi.org/10.1109/JXCDC.2023.3340376","url":null,"abstract":"","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"9 2","pages":"C2-C2"},"PeriodicalIF":2.4,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10416963","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139654742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"HamFET: A High-Performance Subthermionic Transistor Through Incorporating Hybrid Switching Mechanism","authors":"Qianqian Huang;Shaodi Xu;Ru Huang","doi":"10.1109/JXCDC.2023.3338480","DOIUrl":"https://doi.org/10.1109/JXCDC.2023.3338480","url":null,"abstract":"Field-effect transistors (FETs) switched by quantum band-to-band tunneling (BTBT) mechanism, rather than conventional thermionic emission mechanism, are emerging as an exciting device candidate for future ultralow-power electronics due to their exceptional electronic properties of subthermionic subthreshold swing. However, fundamental limitations in drive current have hindered such technology encountering for high-performance and high-speed operations, especially for silicon-based device. Here, we demonstrate a novel pathway of integrating tunneling and thermionic emission mechanisms together, to circumvent their respective limitation and design a hybrid adaptively modulated FET (HamFET) that orients power saving and performance enhancement simultaneously. This transistor architecture, utilizing a nested source configuration without cost or area penalties, exhibits both ultrasteep (subthermionic) subthreshold swing and the largest “on” and “off” current ratio over the state-of-the-art tunneling transistors. Our design methodology of hybrid switching mechanism is also applicable to other mechanism, material, and architecture systems, opening the doors to a range of high-speed application opportunities for ultralow-power but performance-insufficient electronics.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"10 ","pages":"1-7"},"PeriodicalIF":2.4,"publicationDate":"2023-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10336778","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139727434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design Exploration of 14 nm FinFET for Energy-Efficient Cryogenic Computing","authors":"Amol D. Gaidhane;Rakshith Saligram;Wriddhi Chakraborty;Suman Datta;Arijit Raychowdhury;Yu Cao","doi":"10.1109/JXCDC.2023.3330767","DOIUrl":"10.1109/JXCDC.2023.3330767","url":null,"abstract":"Cryogenic operation of CMOS transistors (i.e., cryo-CMOS) effectively brings an ultrasteep subthreshold slope (SS) and ultralow leakage, enabling high energy efficiency with appropriate tuning of threshold voltage and supply voltage. On the other hand, cryo-CMOS suffers from elevated sensitivity to process and voltage variations. To facilitate early-stage design exploration, we develop predictive BSIM-CMG model cards, which are calibrated with 14 nm TCAD simulation and our experimental FinFET data from 300 to 77 K. These models are scalable with temperatures from 300 K down to 77 K, device engineering and variations. Based on them, we benchmark various circuit examples to illustrate the tremendous potential of cryo-CMOS for energy-efficient computing, in the presence of process variations. For logic circuits, such as a canonical critical path, more than \u0000<inline-formula> <tex-math>$15times $ </tex-math></inline-formula>\u0000 reduction in total energy consumption is demonstrated at 77 K for the iso–Delay condition, compared to the operation at the room temperature (RT). The presence of variations only has a marginal impact on energy efficiency, after threshold voltage and supply voltage are adaptively increased. For static noise margin (SNM), it is consistently improved at 77 K. However, the impact of variations on SNM is much more pronounced than that on logic circuits.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"9 2","pages":"108-115"},"PeriodicalIF":2.4,"publicationDate":"2023-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10310237","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135507440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling and Investigating Total Ionizing Dose Impact on FeFET","authors":"Munazza Sayed;Kai Ni;Hussam Amrouch","doi":"10.1109/JXCDC.2023.3325706","DOIUrl":"10.1109/JXCDC.2023.3325706","url":null,"abstract":"This article presents a novel, simulation-based study of the long-term impact of X-ray irradiation on the ferroelectric field effect transistor (FeFET). The analysis is conducted through accurate multiphysics technology CAD (TCAD) simulations and radiation impact on the two FeFET memory states—high-voltage threshold (HVT) and low-voltage threshold (LVT)—is studied. For both the states, we investigate the deterioration of device characteristics, such as threshold voltage shift (\u0000<inline-formula> <tex-math>$Delta V_{text {th}}$ </tex-math></inline-formula>\u0000) and memory window (MW) degradation, resulting from total ionizing dose (TID) exposure between 10 krad/s and 3 Mrad/s. At a dose rate of 10 krad/s, the FeFET is adequately radiation hardened for both HVT and LVT due to negligible change in MW from the baseline, unradiated case. At a dose rate of 3 Mad/s, an MW degradation of 40% is observed, and the greatest contributor is identified as the HVT state, which shows a 0.5-V increase in \u0000<inline-formula> <tex-math>$Delta V_{text {th}}$ </tex-math></inline-formula>\u0000, compared with 0.08 V \u0000<inline-formula> <tex-math>$Delta V_{text {th}}$ </tex-math></inline-formula>\u0000 for LVT at the same dose rate. The difference in radiation responses for HVT and LVT at the same TID is investigated and attributed to the impact of the depolarization electric field (\u0000<inline-formula> <tex-math>$E_{text {dep}}$ </tex-math></inline-formula>\u0000) on the transport of electrons and holes. Consequently, holes form oxide traps that occupy deeper energy levels for HVT compared with LVT, which underlies the \u0000<inline-formula> <tex-math>$V_{text {th}}$ </tex-math></inline-formula>\u0000 shift and MW degradation. The resultant \u0000<inline-formula> <tex-math>$I_{d}$ </tex-math></inline-formula>\u0000–\u0000<inline-formula> <tex-math>$V_{g}$ </tex-math></inline-formula>\u0000 characteristics are in good agreement with the experimental data. Our analysis highlights that the HVT state is sensitive to TID relative to LVT.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"9 2","pages":"143-150"},"PeriodicalIF":2.4,"publicationDate":"2023-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10288360","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135058594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Energy Efficient Logic and Memory Design With Beyond-CMOS Magnetoelectric Spin–Orbit (MESO) Technology Toward Ultralow Supply Voltage","authors":"Rohit Rothe;Hai Li;Dmitri E. Nikonov;Ian A. Young;Kyojin Choo;David Blaauw","doi":"10.1109/JXCDC.2023.3322292","DOIUrl":"10.1109/JXCDC.2023.3322292","url":null,"abstract":"Devices based on the spin as the fundamental computing unit provide a promising beyond-complementary metal–oxide–semiconductor (CMOS) device option, thanks to their energy efficiency and compatibility with CMOS. One such option is a magnetoelectric spin–orbit (MESO) device, an attojoule-class emerging technology promising to extend Moore’s law. This article presents circuit design and optimization techniques, such as device stacking and a canary circuit-based asynchronous clock pulse generation scheme for MESO device technology. With these targeted circuit techniques, the MESO energy efficiency can be improved by \u0000<inline-formula> <tex-math>$sim 1.5times $ </tex-math></inline-formula>\u0000. Novel architectures for arithmetic logic and effective realization of in-memory computing are also proposed that utilize the unique properties of this promising new technology.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"9 2","pages":"124-133"},"PeriodicalIF":2.4,"publicationDate":"2023-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10272647","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136002625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}