IEEE Journal on Exploratory Solid-State Computational Devices and Circuits最新文献_第3页

A Threshold-Voltage Self-Compensated Dual-Gate IGZO TFT Cell for Robust In-Sensor Computing 一种用于传感器内鲁棒计算的阈值电压自补偿双栅IGZO TFT单元

IF 3.1

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-09-22 DOI: 10.1109/JXCDC.2026.3736074

Zhi Li;Zikang Mei;Wei Tang

{"title":"A Threshold-Voltage Self-Compensated Dual-Gate IGZO TFT Cell for Robust In-Sensor Computing","authors":"Zhi Li;Zikang Mei;Wei Tang","doi":"10.1109/JXCDC.2026.3736074","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3736074","url":null,"abstract":"In-sensor computing (ISC) based on amorphous metal-oxide thin-film transistors (TFTs) promises compact, high-density vision chips, yet large-scale integration is vulnerable to process-induced threshold-voltage (<inline-formula> <tex-math>$V_{th}$ </tex-math></inline-formula>) variations that critically degrade computational robustness and accuracy. This work proposes a novel 3T1C (3-Transistor, 1-Capacitor) ISC cell circuit based on photodiode (PD)-gated dual-gate (DG) indium-gallium-zinc-oxide (IGZO) TFTs featuring a <inline-formula> <tex-math>$V_{th}$ </tex-math></inline-formula> self-compensating mechanism for enhanced robustness. The proposed circuit seamlessly integrates memory storage, sensor, and multiply-accumulate (MAC) operations into a single compact cell with a self-compensated sense TFT introduced to effectively suppress the <inline-formula> <tex-math>$V_{th}$ </tex-math></inline-formula> variation during the computing phase. Using a neural-network-based device model, SPICE simulations to validate circuit functionality are performed, presenting a <inline-formula> <tex-math>$2times $ </tex-math></inline-formula> to <inline-formula> <tex-math>$3times $ </tex-math></inline-formula> reduction in computing current variation compared to uncompensated baselines, along with excellent MAC linearity. System-level evaluation of a VGG8 network on CIFAR-10 demonstrates negligible accuracy loss relative to an ideal software implementation. This work validates the feasibility of highly accurate robust ISC on inherently large-scale TFT arrays, offering a practical path toward large-area, low-cost ISC arrays for edge intelligence applications.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"214-222"},"PeriodicalIF":3.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11703610","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149130989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Physics-Guided Active Learning and Geometry-Aware Electrothermal Screening of Semiconductor Devices: A GaN Case Study 物理引导的主动学习和几何感知半导体器件的电热筛选：GaN案例研究

IF 3.1

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-09-22 DOI: 10.1109/JXCDC.2026.3736280

Ayoub Sadeghi;Leonid Popryho;Inna Partin-Vaisband

{"title":"Physics-Guided Active Learning and Geometry-Aware Electrothermal Screening of Semiconductor Devices: A GaN Case Study","authors":"Ayoub Sadeghi;Leonid Popryho;Inna Partin-Vaisband","doi":"10.1109/JXCDC.2026.3736280","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3736280","url":null,"abstract":"Exploring high-dimensional semiconductor device design spaces under coupled electrothermal constraints remains challenging, particularly in 3-D heterogeneous systems with tightly coupled electrical, thermal, and integration requirements. Conventional TCAD-driven exploration is physically accurate but computationally expensive and offers limited insight into governing parameters. This work presents physics-guided active learning trigate optimization (PALTO), a physics-guided active-learning framework for data-efficient design space exploration, combining ensemble surrogate modeling, uncertainty-driven sampling, and diversity-aware selection to reduce reliance on exhaustive TCAD simulations while preserving predictive fidelity. Using multichannel trigate GaN devices as a case study, PALTO identifies Pareto-optimal configurations. A geometry-aware electrothermal scaling methodology is further introduced to evaluate multifin scalability using compact metrics capturing electrostatic activation, thermal vulnerability, and Joule-stress degradation. This analysis—corroborated by feature-importance ranking—identifies GaN channel thickness as a dominant parameter governing electrothermal scalability. Geometry-derived indicators are further used to organize Pareto-selected configurations according to relative electrothermal scaling tendencies without additional high-fin-count TCAD simulations. Results show that stronger barrier activation improves single-fin current but causes earlier electrothermal saturation, whereas GaN-dominant structures exhibit improved high-fin scalability.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"231-239"},"PeriodicalIF":3.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11703620","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149131754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

P-Dits for the Frequency Assignment Problem With Transmitter Deactivation in Dense Environments 密集环境下发射机失活频率分配问题的P-Dits

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-03-07 DOI: 10.1109/JXCDC.2026.3690563

Christian Duffee;Jordan Athas;Igor Kadota;Randall Berry;Pedram Khalili Amiri

{"title":"P-Dits for the Frequency Assignment Problem With Transmitter Deactivation in Dense Environments","authors":"Christian Duffee;Jordan Athas;Igor Kadota;Randall Berry;Pedram Khalili Amiri","doi":"10.1109/JXCDC.2026.3690563","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3690563","url":null,"abstract":"The frequency assignment problem is a nondeterministic polynomial-time hard (NP-hard) optimization problem concerning the assignment of frequency channels to wireless transmitters. Typically, the aim is to minimize interference between transmitters while maintaining a high level of service. In this work, the use of probabilistic d-dimensional bits, or p-dits, for this task is considered. These are stochastic elements that oscillate between discrete states that lie in a multidimensional space. Here, each dimension corresponds to an allowed wireless channel. In addition, a special “0” state exists which corresponds to a disabled and consequently completely noninterfering transmitter. Each transmitter maps to a single p-dit that undergoes repeatable stochastic updates. The p-dit influences the probability distributions of its neighbors, biasing them toward noninterfering states. To provide a realistic and varied dataset, geospatial data for a medium-sized city were used. A simple greedy, Tabu-style, DSatur-style, a traditional p-bit-based probabilistic Ising machine (PIM) solver, and the proposed p-dit-based PIM solver were tasked with finding an assignment, which penalized both deactivated transmitters and interference on two-, three-, and four-wireless-channel problems. Overall, for the same nontrivially short runtime budgets, the p-dit PIM solver found the highest quality solutions of all the approaches explored.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"78-85"},"PeriodicalIF":2.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11511717","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148003679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A CMOS Probabilistic Computing Chip With Hardware-Aware Learning 一种具有硬件感知学习的CMOS概率计算芯片

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-03-01 DOI: 10.1109/JXCDC.2026.3689506

Jinesh Jhonsa;William Whitehead;Yihao Wu;David Mccarthy;Shuvro Chowdhury;Kerem Y. Camsari;Luke Theogarajan

{"title":"A CMOS Probabilistic Computing Chip With Hardware-Aware Learning","authors":"Jinesh Jhonsa;William Whitehead;Yihao Wu;David Mccarthy;Shuvro Chowdhury;Kerem Y. Camsari;Luke Theogarajan","doi":"10.1109/JXCDC.2026.3689506","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3689506","url":null,"abstract":"This work demonstrates a compact probabilistic computing system based on a physics-inspired probabilistic bit (p-bit) architecture with 440 interacting spins configured in a chimera graph and occupying 0.44 mm2 of silicon area. Area efficiency is achieved through a current-mode neuron update circuit and a mixed-signal design approach that integrates pitch-matched standard-cell analog blocks with digital logic and a shared power supply network. Device mismatch and process variations arising from this tightly coupled mixed-signal implementation are addressed using a hardware-aware contrastive divergence training framework. By incorporating nonideal circuit behavior directly into the training loop, the system achieves reliable stochastic dynamics without requiring per-device calibration. Measurement results validate robust probabilistic operation across all spins. The chip is evaluated on probabilistic logic functions, including logic gates and full adders, and on combinatorial optimization problems such as max cut. These results demonstrate that learning-enabled compensation of hardware nonidealities enables scalable probabilistic computing architectures. The proposed system demonstrates effective cross-layer codesign across circuit, architectural, and algorithmic levels, supporting emerging nonvon Neumann computing paradigms.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"86-94"},"PeriodicalIF":2.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11503224","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148003680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A3D-MoE: Acceleration of Large Language Models With Mixture of Experts via 3-D Heterogeneous Integration A3D-MoE：通过三维异构集成加速专家混合的大型语言模型

IF 3.1

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-07-16 DOI: 10.1109/JXCDC.2026.3713957

Wei-Hsing Huang;Janak Sharda;Cheng-Jhih Shih;Yuyao Kong;Faaiq Waqar;Pin-Jun Chen;Yingyan Lin;Shimeng Yu

{"title":"A3D-MoE: Acceleration of Large Language Models With Mixture of Experts via 3-D Heterogeneous Integration","authors":"Wei-Hsing Huang;Janak Sharda;Cheng-Jhih Shih;Yuyao Kong;Faaiq Waqar;Pin-Jun Chen;Yingyan Lin;Shimeng Yu","doi":"10.1109/JXCDC.2026.3713957","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3713957","url":null,"abstract":"Conventional large language models (LLMs) have large parameter sets, making inference costly and energy-intensive; mixture-of-experts (MoEs) mitigates this by activating fewer weights per token, but fine-grained MoE LLMs still face runtime workload variability, inefficient conventional scheduling, and high bandwidth memory (HBM) loading energy/bandwidth demands. A3D-MoE addresses these with 3-D heterogeneous integration to improve memory bandwidth and reduce NoC overhead/energy; a 3-D-systolic array with V-Cache reuse and unified 3-D dataflow to optimize hardware utilization across workloads; a hardware resource-aware operation fusion scheduler (HR-OFS) that fuses attention/MoE operations to boost performance; and MoE Score-Aware HBM access reduction with even–odd expert placement (MoE-HBMR-EOP) to reduce HBM access/bandwidth demand. Evaluations show <inline-formula> <tex-math>$1.8times $ </tex-math></inline-formula>–<inline-formula> <tex-math>$2times $ </tex-math></inline-formula> lower latency, <inline-formula> <tex-math>$2times $ </tex-math></inline-formula>–<inline-formula> <tex-math>$4times $ </tex-math></inline-formula> lower energy, and <inline-formula> <tex-math>$1.44times $ </tex-math></inline-formula>–<inline-formula> <tex-math>$1.8times $ </tex-math></inline-formula> higher throughput than the state-of-the-art.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"176-184"},"PeriodicalIF":3.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11611883","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148628165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

1-Transistor-Dynamic Random Access Memory as Reservoir for Temporal Signal Processing 晶体管动态随机存储器作为时间信号处理的储存库

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-03-06 DOI: 10.1109/JXCDC.2026.3690766

Md Yasir Bashir;Lalith Adithya Sai C.;Shubham Sahay

{"title":"1-Transistor-Dynamic Random Access Memory as Reservoir for Temporal Signal Processing","authors":"Md Yasir Bashir;Lalith Adithya Sai C.;Shubham Sahay","doi":"10.1109/JXCDC.2026.3690766","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3690766","url":null,"abstract":"Reservoir computing (RC), a computational paradigm inspired by the recurrent neural networks (RNNs), offers a promising framework for efficient temporal processing with minimal training overhead. Hardware implementation of RC primitive requires devices that exhibit short-term memory, nonlinearity, and energy-efficient state-switching dynamics. While emerging nonvolatile memory (eNVM) technologies have been explored as physical reservoirs, their limited endurance and wafer-scale fabrication challenges hinder widespread application for real-time edge-compatible RC systems. In contrast, 1-transistor-dynamic random access memories (1T-DRAMs) have recently gained significant attention owing to their high scalability, low footprint, and high endurance. In this work, we propose the use of 1T-DRAMs as physical reservoirs for computing and temporal signal processing. We show that the inherent charge storage and its temporal decay in the body of 1T-DRAMs owing to the dynamic recombination efficiently emulates the fading (short-term) memory behavior, making it well-suited for RC. Furthermore, networks of the 1T-DRAM physical reservoirs achieve classification accuracy of 82.46% and 85.02% on reduced MNIST and Weizmann human action dataset, respectively.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"120-128"},"PeriodicalIF":2.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11510294","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148171938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comparative Analysis of Sense Amplifier Circuits for Hybrid CMOS-MTJ CIM Architecture CMOS-MTJ - CIM混合结构感测放大电路的比较分析

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-03-05 DOI: 10.1109/JXCDC.2026.3690460

Yashvardhan Singh;Siddharth Penumatsa;Prashanth Barla

{"title":"Comparative Analysis of Sense Amplifier Circuits for Hybrid CMOS-MTJ CIM Architecture","authors":"Yashvardhan Singh;Siddharth Penumatsa;Prashanth Barla","doi":"10.1109/JXCDC.2026.3690460","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3690460","url":null,"abstract":"Spin-transfer torque magnetic tunnel junction (STT-MTJ) is widely recognized as a promising device for computation-in-memory (CIM) architecture due to its advantages, such as simple nonvolatile structure, CMOS compatibility, and scalability. In spite of the advantages, achieving reliable and efficient sensing of STT-MTJ remains a design challenge. This work presents a comparative evaluation and operational assessment of six contemporary current-mode sense-amplifier (SA) circuits for STT-MTJ, namely the precharge sensing amplifier (PCSA), improved PCSA (IPCSA), separated PCSA (SPCSA), reliability enhanced separated PCSA (RESPCSA), reliability-enhanced differential SA (REDSA), and high reliability SA (HRSA) used in hybrid CMOS-MTJ for CIM architecture. The proposed benchmarking framework analyses critical performance metrics, such as power consumption, sensing margin, read delay, transistor count, and read error probability for all the SA circuits. In addition, assessment of tolerance against process- and device-level variations of these SAs has been conducted with an extensive parametric sweep analysis, considering tunnel magnetoresistance (TMR), oxide thickness variations, and transistor sizing using a 1000-run Monte Carlo (MC) simulation. Based on these insights, our study outlines design tradeoffs and provides recommendations for selecting a suitable SA circuit for hybrid STT-MTJ-based CIM structures.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"95-103"},"PeriodicalIF":2.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11506373","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148003681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

LUT-Based Convolutional Tsetlin Machine Accelerator With Dynamic Clause Scaling for Resources-Constrained FPGAs 基于lut的动态子句缩放卷积Tsetlin机器加速器在资源受限fpga中的应用

IF 2.7

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-03-23 DOI: 10.1109/JXCDC.2026.3676833

Rashed Al Amin;Roman Obermaisser

{"title":"LUT-Based Convolutional Tsetlin Machine Accelerator With Dynamic Clause Scaling for Resources-Constrained FPGAs","authors":"Rashed Al Amin;Roman Obermaisser","doi":"10.1109/JXCDC.2026.3676833","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3676833","url":null,"abstract":"The rapid growth of machine learning (ML) workloads, particularly in computer vision applications, has significantly increased computational and energy demands in modern electronic systems, motivating the use of hardware accelerators to offload processing from general-purpose processors. Despite advances in computationally efficient ML models, achieving energy-efficient inference on resource-constrained edge devices remains a significant challenge. The Tsetlin machine (TM) has emerged as an attractive alternative for image classification due to its high throughput and inherently energy-efficient learning paradigm. However, existing TM-based hardware accelerators struggle to balance classification accuracy and energy efficiency, limiting their practical deployment at the edge. This article presents a resource- and energy-efficient convolutional TM (CTM) accelerator with dynamic clause scaling, optimized explicitly for edge field-programmable gate array (FPGA) platforms. The proposed architecture employs LUT-based pipelining and targeted resource-optimization techniques to minimize FPGA resource utilization while maintaining high-energy efficiency and performance. The accelerator is implemented on a Xilinx Zybo-Z20 FPGA and evaluated using the MNIST, Fashion-MNIST (FMNIST), and Kuzushiji-MNIST (KMNIST) datasets, achieving classification accuracies of 97.78%, 85.53%, and 88.54%, respectively, with an energy consumption of up to <inline-formula> <tex-math>$0.3~mu $ </tex-math></inline-formula>J per image classification. Compared with state-of-the-art CTM accelerators, the proposed design achieves up to <inline-formula> <tex-math>$40times $ </tex-math></inline-formula> improvements in resource and energy efficiency, demonstrating its suitability for real-time image and pattern classification on edge FPGA-based systems.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"45-55"},"PeriodicalIF":2.7,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11454583","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147606329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Leveraging a Passive MRAM Crossbar for Hardware-in-the-Loop and Continual learning 利用被动MRAM交叉杆实现硬件在环和持续学习

IF 3.1

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-06-09 DOI: 10.1109/JXCDC.2026.3702001

M. Drouhin;M. Grelier;M. Deroo;Y. Sassi;E. Monteblanco;N. Davila;G. Mihajlović;R. V. Chopdekar;T. S. Santos;J. A. Katine;D. Ravelosona

{"title":"Leveraging a Passive MRAM Crossbar for Hardware-in-the-Loop and Continual learning","authors":"M. Drouhin;M. Grelier;M. Deroo;Y. Sassi;E. Monteblanco;N. Davila;G. Mihajlović;R. V. Chopdekar;T. S. Santos;J. A. Katine;D. Ravelosona","doi":"10.1109/JXCDC.2026.3702001","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3702001","url":null,"abstract":"Artificial neural networks (ANNs) have enabled major advances in artificial intelligence, yet their growing computational and energy demands challenge conventional von Neumann architectures due to the costly separation of memory and processing. In-memory computing has emerged as a promising solution, particularly through memristive crossbar arrays capable of performing multiply-and-accumulate operations directly within memory. Among nonvolatile memory technologies, magnetic tunnel junctions, the core elements of MRAM, offer high endurance, nonvolatility, and CMOS compatibility, making them attractive candidates for neuromorphic systems. In this work, we report inference results on a <inline-formula> <tex-math>$15 times 15$ </tex-math></inline-formula> MRAM crossbar, benchmarking experimental measurements against numerical simulations. We further demonstrate hardware-in-the-loop (HIL) training and experimentally validate metaplasticity mechanisms enabling continual learning on simple tasks. These results highlight the potential of MRAM-based in-memory architectures for adaptive, energy-efficient, and scalable artificial intelligence (AI) hardware.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"129-134"},"PeriodicalIF":3.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11556473","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148443350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Nanoelectromechanically Gated Gain Cell eDRAM 纳米机电门控增益单元eDRAM

IF 3.1

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2026-01-01 Epub Date: 2026-10-06 DOI: 10.1109/JXCDC.2026.3717204

Collin P. Finnan;Choong-Ho Rhee;Tahir Ghani;Tsu-Jae King-Liu

{"title":"Nanoelectromechanically Gated Gain Cell eDRAM","authors":"Collin P. Finnan;Choong-Ho Rhee;Tahir Ghani;Tsu-Jae King-Liu","doi":"10.1109/JXCDC.2026.3717204","DOIUrl":"https://doi.org/10.1109/JXCDC.2026.3717204","url":null,"abstract":"The memory wall and the slowdown of static random access memory (SRAM) scaling have renewed interest in gain-cell embedded dynamic random access memory (DRAM). While gain cells offer high density and energy efficiency, they suffer from limited retention, parasitic coupling, and the need for boosted write voltages. This work introduces a nanoelectromechanically gated gain cell for embedded DRAM. The simulated cell eliminates subthreshold leakage and write disturb from parasitic capacitance present in conventional 2T and 3T gain cells, significantly improving retention. In addition, the proposed cell has a write port implemented in back-end-of-line layers to conserve cell layout area relative to transistor-only implementations. A cell size of <inline-formula> <tex-math>$0.072~mu $ </tex-math></inline-formula>m2 is projected for a 2 nm process technology to provide approximately <inline-formula> <tex-math>$3times $ </tex-math></inline-formula> higher cell density than SRAM. Using SPICE simulation, the proposed cell exhibits a retention time of 300 ms at <inline-formula> <tex-math>$125~^{circ } $ </tex-math></inline-formula>C while maintaining sub-1 ns read latency in a <inline-formula> <tex-math>$256~times ~128$ </tex-math></inline-formula> array with significantly smaller static power than SRAM. The proposed bit cell operates at CMOS-compatible voltages and requires minimal process modification from a standard CMOS foundry process, introducing no novel materials.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"223-230"},"PeriodicalIF":3.1,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11721447","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149130945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0