IEEE Journal on Exploratory Solid-State Computational Devices and Circuits最新文献

{"title":"HamFET: A High-Performance Subthermionic Transistor Through Incorporating Hybrid Switching Mechanism","authors":"Qianqian Huang;Shaodi Xu;Ru Huang","doi":"10.1109/JXCDC.2023.3338480","DOIUrl":"https://doi.org/10.1109/JXCDC.2023.3338480","url":null,"abstract":"Field-effect transistors (FETs) switched by quantum band-to-band tunneling (BTBT) mechanism, rather than conventional thermionic emission mechanism, are emerging as an exciting device candidate for future ultralow-power electronics due to their exceptional electronic properties of subthermionic subthreshold swing. However, fundamental limitations in drive current have hindered such technology encountering for high-performance and high-speed operations, especially for silicon-based device. Here, we demonstrate a novel pathway of integrating tunneling and thermionic emission mechanisms together, to circumvent their respective limitation and design a hybrid adaptively modulated FET (HamFET) that orients power saving and performance enhancement simultaneously. This transistor architecture, utilizing a nested source configuration without cost or area penalties, exhibits both ultrasteep (subthermionic) subthreshold swing and the largest “on” and “off” current ratio over the state-of-the-art tunneling transistors. Our design methodology of hybrid switching mechanism is also applicable to other mechanism, material, and architecture systems, opening the doors to a range of high-speed application opportunities for ultralow-power but performance-insufficient electronics.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2023-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10336778","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139727434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design Exploration of 14 nm FinFET for Energy-Efficient Cryogenic Computing","authors":"Amol D. Gaidhane;Rakshith Saligram;Wriddhi Chakraborty;Suman Datta;Arijit Raychowdhury;Yu Cao","doi":"10.1109/JXCDC.2023.3330767","DOIUrl":"10.1109/JXCDC.2023.3330767","url":null,"abstract":"Cryogenic operation of CMOS transistors (i.e., cryo-CMOS) effectively brings an ultrasteep subthreshold slope (SS) and ultralow leakage, enabling high energy efficiency with appropriate tuning of threshold voltage and supply voltage. On the other hand, cryo-CMOS suffers from elevated sensitivity to process and voltage variations. To facilitate early-stage design exploration, we develop predictive BSIM-CMG model cards, which are calibrated with 14 nm TCAD simulation and our experimental FinFET data from 300 to 77 K. These models are scalable with temperatures from 300 K down to 77 K, device engineering and variations. Based on them, we benchmark various circuit examples to illustrate the tremendous potential of cryo-CMOS for energy-efficient computing, in the presence of process variations. For logic circuits, such as a canonical critical path, more than \u0000<inline-formula> <tex-math>$15times $ </tex-math></inline-formula>\u0000 reduction in total energy consumption is demonstrated at 77 K for the iso–Delay condition, compared to the operation at the room temperature (RT). The presence of variations only has a marginal impact on energy efficiency, after threshold voltage and supply voltage are adaptively increased. For static noise margin (SNM), it is consistently improved at 77 K. However, the impact of variations on SNM is much more pronounced than that on logic circuits.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2023-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10310237","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135507440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling and Investigating Total Ionizing Dose Impact on FeFET","authors":"Munazza Sayed;Kai Ni;Hussam Amrouch","doi":"10.1109/JXCDC.2023.3325706","DOIUrl":"10.1109/JXCDC.2023.3325706","url":null,"abstract":"This article presents a novel, simulation-based study of the long-term impact of X-ray irradiation on the ferroelectric field effect transistor (FeFET). The analysis is conducted through accurate multiphysics technology CAD (TCAD) simulations and radiation impact on the two FeFET memory states—high-voltage threshold (HVT) and low-voltage threshold (LVT)—is studied. For both the states, we investigate the deterioration of device characteristics, such as threshold voltage shift (\u0000<inline-formula> <tex-math>$Delta V_{text {th}}$ </tex-math></inline-formula>\u0000) and memory window (MW) degradation, resulting from total ionizing dose (TID) exposure between 10 krad/s and 3 Mrad/s. At a dose rate of 10 krad/s, the FeFET is adequately radiation hardened for both HVT and LVT due to negligible change in MW from the baseline, unradiated case. At a dose rate of 3 Mad/s, an MW degradation of 40% is observed, and the greatest contributor is identified as the HVT state, which shows a 0.5-V increase in \u0000<inline-formula> <tex-math>$Delta V_{text {th}}$ </tex-math></inline-formula>\u0000, compared with 0.08 V \u0000<inline-formula> <tex-math>$Delta V_{text {th}}$ </tex-math></inline-formula>\u0000 for LVT at the same dose rate. The difference in radiation responses for HVT and LVT at the same TID is investigated and attributed to the impact of the depolarization electric field (\u0000<inline-formula> <tex-math>$E_{text {dep}}$ </tex-math></inline-formula>\u0000) on the transport of electrons and holes. Consequently, holes form oxide traps that occupy deeper energy levels for HVT compared with LVT, which underlies the \u0000<inline-formula> <tex-math>$V_{text {th}}$ </tex-math></inline-formula>\u0000 shift and MW degradation. The resultant \u0000<inline-formula> <tex-math>$I_{d}$ </tex-math></inline-formula>\u0000–\u0000<inline-formula> <tex-math>$V_{g}$ </tex-math></inline-formula>\u0000 characteristics are in good agreement with the experimental data. Our analysis highlights that the HVT state is sensitive to TID relative to LVT.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2023-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10288360","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135058594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Energy Efficient Logic and Memory Design With Beyond-CMOS Magnetoelectric Spin–Orbit (MESO) Technology Toward Ultralow Supply Voltage","authors":"Rohit Rothe;Hai Li;Dmitri E. Nikonov;Ian A. Young;Kyojin Choo;David Blaauw","doi":"10.1109/JXCDC.2023.3322292","DOIUrl":"10.1109/JXCDC.2023.3322292","url":null,"abstract":"Devices based on the spin as the fundamental computing unit provide a promising beyond-complementary metal–oxide–semiconductor (CMOS) device option, thanks to their energy efficiency and compatibility with CMOS. One such option is a magnetoelectric spin–orbit (MESO) device, an attojoule-class emerging technology promising to extend Moore’s law. This article presents circuit design and optimization techniques, such as device stacking and a canary circuit-based asynchronous clock pulse generation scheme for MESO device technology. With these targeted circuit techniques, the MESO energy efficiency can be improved by \u0000<inline-formula> <tex-math>$sim 1.5times $ </tex-math></inline-formula>\u0000. Novel architectures for arithmetic logic and effective realization of in-memory computing are also proposed that utilize the unique properties of this promising new technology.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2023-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10272647","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136002625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"True Random Number Generator Based on RRAM-Bias Current Starved Ring Oscillator","authors":"D. Arumí;S. Manich;A. Gómez-Pau;R. Rodríguez-Montañés;M. B. González;F. Campabadal","doi":"10.1109/JXCDC.2023.3320056","DOIUrl":"https://doi.org/10.1109/JXCDC.2023.3320056","url":null,"abstract":"This work presents a resistive random access memory (RRAM)-bias current-starved ring oscillator (CSRO) as true random number generator (TRNG), where the cycle-to-cycle variability of an RRAM device is exploited as source of randomness. A simple voltage divider composed of this RRAM and a resistor is considered to bias the gate terminal of the extra transistor of every current starved (CS) inverter of the ring oscillator (RO). In this way, the delay of the inverters is modified, deriving an unpredictable oscillation frequency every time the RRAM switches to the high resistance state (HRS). The oscillation frequency is finally leveraged to extract the sequence of random bits. The design is simple and adds low area overhead. Experimental measurements are performed to analyze the cycle-to-cycle variability in the HRS. The very same measurements are subsequently used to validate the TRNG by means of electrical simulations. The obtained results passed all the National Institute of Standards and Technology randomness tests (NIST) tests without the need for postprocessing.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2023-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10268070","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"109229885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"XNOR-VSH: A Valley-Spin Hall Effect-Based Compact and Energy-Efficient Synaptic Crossbar Array for Binary Neural Networks","authors":"Karam Cho;Akul Malhotra;Sumeet Kumar Gupta","doi":"10.1109/JXCDC.2023.3320677","DOIUrl":"10.1109/JXCDC.2023.3320677","url":null,"abstract":"Binary neural networks (BNNs) have shown an immense promise for resource-constrained edge artificial intelligence (AI) platforms. However, prior designs typically either require two bit-cells to encode signed weights leading to an area overhead, or require complex peripheral circuitry. In this article, we address this issue by proposing a compact and low power in-memory computing (IMC) of XNOR-based dot products featuring signed weight encoding in a single bit-cell. Our approach utilizes valley-spin Hall (VSH) effect in monolayer tungsten di-selenide to design an XNOR bit-cell (named “XNOR-VSH”) with differential storage and access-transistor-less topology. We co-optimize the proposed VSH device and a memory array to enable robust in-memory dot product computations between signed binary inputs and signed binary weights with sense margin (SM)\u0000<inline-formula> <tex-math>$1 ~mu text{A}$ </tex-math></inline-formula>\u0000. Our results show that the proposed XNOR-VSH array achieves 4.8%–9.0% and 37%–63% lower IMC latency and energy, respectively, with 49%–64% smaller area compared to spin-transfer-torque (STT)-magnetic random access memory (MRAM) and spin-orbit-torque (SOT)-MRAM based XNOR-arrays. We also present the impact of hardware non-idealities and process variations in XNOR-VSH on system-level accuracy for the trained ResNet-18 BNNs using the CIFAR-10 dataset.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2023-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10268108","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135845097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Many-Body Effects-Based Invertible Logic With a Simple Energy Landscape and High Accuracy","authors":"Yihan He;Chao Fang;Sheng Luo;Gengchiau Liang","doi":"10.1109/JXCDC.2023.3320230","DOIUrl":"https://doi.org/10.1109/JXCDC.2023.3320230","url":null,"abstract":"Inspired by many-body effects, we propose a novel design for Boltzmann machine (BM)-based invertible logic (IL) using probabilistic bits (p-bits). A CMOS-based XNOR gate is derived to serve as the hardware implementation of many-body interactions, and an IL family is built based on this design. Compared to the conventional two-body-based design framework, the many-body-based design enables compact configuration and provides the simplest binarized energy landscape for fundamental IL gates; furthermore, we demonstrate the composability of the many-body-based IL circuit by merging modular building blocks into large-scale integer factorizers (IFs). To optimize the energy landscape of large-scale combinatorial IL circuits, we introduce degeneracy in energy levels, which enlarges the probabilities for the lowest states. Circuit simulations of our IFs reveal a significant boost in factorization accuracy. An example of a 2- \u0000<inline-formula> <tex-math>$times2$ </tex-math></inline-formula>\u0000-bit IF demonstrated an increment of factorization accuracy from 64.99% to 91.44% with a reduction in the number of energy levels from 32 to 9. Similarly, our 6- \u0000<inline-formula> <tex-math>$times6$ </tex-math></inline-formula>\u0000-bit IF increases the accuracy from 4.430% to 83.65% with the many-body design. Overall, the many-body-based design scheme provides promising results for future IL circuit designs.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2023-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/10288180/10266315.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49964659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling and Evaluation of Echo-State Networks Using Spin Torque Nano-Oscillators","authors":"Siyuan Qian;Shaloo Rakheja","doi":"10.1109/JXCDC.2023.3317240","DOIUrl":"10.1109/JXCDC.2023.3317240","url":null,"abstract":"An echo state network (ESN), capable of processing time-series data with high accuracy, is designed and benchmarked using spin torque nano-oscillators (STNOs) with easy-plane anisotropy. An ESN belongs to the category of reservoir computers, where the reservoir comprises a randomly initialized, recurrently connected, and untrained pool of neurons and acts as a high-dimensional expansion of the input signal. The readout function is used to glean a meaningful output representation. Here, we use STNOs as the basic building block of the ESN and apply the ESN to predict the Mackey–Glass (MG) time-series data. The design parameters of the STNO and the input data representation are selected to yield prediction errors as low as \u0000<inline-formula> <tex-math>$4times 10^{-3}$ </tex-math></inline-formula>\u0000. We also quantify the short-term memory (STM) and the parity-check (PC) capacity of the ESN and obtain metrics that are comparable to or better than existing spintronics-based ESNs, as well as ESNs employing “tanh” neurons. The peak STM is found to be approximately 8.8, while the peak PC capacity is found to be approximately 3.9. The impacts of thermal fluctuations and process variability on ESN performance are systematically quantified. Although the ESN’s prediction and memory capability remain robust with temperature variations, a 10% variation in the dimensions of the STNO free layer can lead to around 40% increase in its prediction error for the MG time-series data.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2023-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10255553","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135551560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The Impact of Analog-to-Digital Converter Architecture and Variability on Analog Neural Network Accuracy","authors":"Matthew Spear;Joshua E. Kim;Christopher H. Bennett;Sapan Agarwal;Matthew J. Marinella;T. Patrick Xiao","doi":"10.1109/JXCDC.2023.3315134","DOIUrl":"10.1109/JXCDC.2023.3315134","url":null,"abstract":"The analog-to-digital converter (ADC) is not only a key component in analog in-memory computing (IMC) accelerators but also a bottleneck for the efficiency and accuracy of these systems. While the tradeoffs between power consumption, latency, and area in ADC design are well studied, it is relatively unknown which ADC implementations are optimal for algorithmic accuracy, particularly for neural network inference. We explore the design space of the ADC with a focus on accuracy, investigating the sensitivity of neural network outputs to component variability inside the ADC and how this sensitivity depends on the ADC architecture. The compact models of the pipeline, cyclic, successive-approximation-register (SAR) and ramp ADCs are developed, and these models are used in a system-level accuracy simulation of analog neural network inference. Our results show how the accuracy on a complex image recognition benchmark (ResNet50 on ImageNet) depends on the capacitance mismatch, comparator offset, and effective number of bits (ENOB) for each of the four ADC architectures. We find that robustness to component variations depends strongly on the ADC design and that inference accuracy is particularly sensitive to the value-dependent error characteristics of the ADC, which cannot be captured by the conventional ENOB precision metric.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2023-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10250846","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135402296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Stuck-at Faults Tolerance and Recovery in MLP Neural Networks Using Imperfect Emerging CNFET Technology","authors":"An Qi Zhang;Amr M. S. Tosson;Dylan Ma;Ryan Fang;Lan Wei","doi":"10.1109/JXCDC.2023.3313127","DOIUrl":"10.1109/JXCDC.2023.3313127","url":null,"abstract":"Devices using emerging technologies and materials with the potential to outperform their silicon counterpart are actively explored in search of ways to extend Moore’s law. Among these technologies, low dimensional channel materials (LDMs) devices, such as carbon nanotube field-effect transistors (CNFETs), are promising to eventually outperform silicon CMOS. As these technologies are in their early development stages, their devices still suffer from high levels of defects and variations, thus unsuitable for nowadays general-purpose applications. On the other hand, applications with inherent error resilience and high-performance demands would suppress the impact of process imperfection and benefit from the performance boost. These applications, including image processing and machine learning through neural networks, would be the ideal targets for adopting these new emerging technologies even in their early stage of technology and process development. In this article, the effects of stuck-at faults in CNFET static random access memory (SRAM)-based multilayer perceptron (MLP) neural network are investigated. The impacts of various fault patterns are analyzed. Several fault recovery techniques are introduced, and their effectiveness is analyzed under different scenarios. With the proposed recovery techniques, the system can recover and tolerate a high level of stuck-at faults up to 40%, paving the path to adopt the early-stage and faulty emerging devices technologies in such high-demand applications.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2023-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10246789","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135361608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}