IEEE Journal on Exploratory Solid-State Computational Devices and Circuits最新文献

{"title":"A Bit-Cell Failure Analysis Framework for Ferroelectric Field-Effect Transistor-Based Memories","authors":"Jianze Wang;Wei Zhang;Xuanyao Fong","doi":"10.1109/JXCDC.2025.3616007","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3616007","url":null,"abstract":"The ferroelectric field-effect transistor (FeFET) is a promising memory device technology due to desirable attributes, such as fast access times, high memory cell density, good endurance, compatibility with CMOS process, and impressive scalability. While previous research has explored the impact of process variations at the device level, their effects on circuit behavior have not been comprehensively investigated due to a lack of a framework for analyzing FeFET bit-cell failures at the circuit level, which we present in this work. We studied the process parameters, including ferroelectric (FE) layer thickness, channel length, channel width, and effective oxide thickness of an FeFET bit cell. The correlations of each failure event and the write pulse voltage and write pulsewidth are studied. Our results show that the voltage applied on the FeFET bit cell dominates the performance of the bit cell for both write and read operations.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"123-130"},"PeriodicalIF":2.7,"publicationDate":"2025-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11185162","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145405385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Beyond Backside Power: Backside Signal Routing as Technology Booster for Standard-Cell Scaling","authors":"Anup Ashok Kedilaya;Sirish Oruganti;Nishant Gupta;Xiuhao Zhang;Ilya Karpov;Mark A. Anders;Jaydeep P. Kulkarni","doi":"10.1109/JXCDC.2025.3617784","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3617784","url":null,"abstract":"Advances in process technology enabling backside metals (BSMs) and contacts offer new design–technology co-optimization (DTCO) opportunities to further enhance power, performance, and area gains (PPA) in sub-3-nm nodes. This work exploits backside (BS) contact technology within standard cells to extend both signal and clock routing to BSM layers, enabling standard-cell height reduction options. We design electrically equivalent (EEQ) standard cells with multiple layout variants based on front versus BS pin access, achieving a 2-M0-Track height reduction in 3-nm gate-all-around field-effect transistor (GAAFET) technology. Experimental evaluation across representative industrial benchmarks—including high-performance CPUs, GPUs, and general-purpose systems-on-chip (SoCs) demonstrates significant benefits. Cell height reduction delivers up to 35% area savings and 10%–15% total power reduction for GPU and GP-SoC designs. For high-performance CPUs, maximum performance improves by 15% at iso-power compared to backside power with buried power rails (BSBPR). Incorporating BS signal routing with cell height reduction also reduces worst case IR drop by 32% relative to BSBPR. These results show that BS clock (BSCLK) and signal routing represent the next phase of technology innovation beyond BS power delivery, enabling continued standard-cell scaling, improved intracell and intercell routability, and generational PPA gains while maintaining similar core transistor geometries in sub-3-nm technologies.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"107-115"},"PeriodicalIF":2.7,"publicationDate":"2025-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11192533","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145352255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"3-D Stacked HBM and Compute Accelerators for LLM: Optimizing Thermal Management and Power Delivery Efficiency","authors":"Janak Sharda;Madison Manley;Jungyoun Kwak;Chinsung Park;Muhannad Bakir;Shimeng Yu","doi":"10.1109/JXCDC.2025.3617298","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3617298","url":null,"abstract":"Advanced packaging is becoming essential for designing hardware accelerators for large language models (LLMs). Different architectures, such as 2.5-D integration of memory with logic, have been proposed; however, the bandwidth limits the throughput of the complete system. Recent works have proposed memory on logic systems, where high bandwidth memory (HBM) can be 3-D stacked on top of logic to improve the throughput by <inline-formula> <tex-math>$64times $ </tex-math></inline-formula> and energy efficiency by <inline-formula> <tex-math>$3times $ </tex-math></inline-formula>. However, the high-power consumption of logic dies and the high thermal resistance of HBM can result in thermal and power delivery challenges in such heterogeneously integrated stacks. In this work, we explore various design configurations, such as logic-on-memory and memory-on-logic, and consider some hybrid configurations. Furthermore, accurate modeling of DRAM dies is performed, and mitigation strategies are proposed to further improve the throughput by 16% for memory-on-logic, reduce the high resistive (IR) drop for logic-on-memory system by 640 mV, and get <inline-formula> <tex-math>$4times $ </tex-math></inline-formula> higher throughput for a hybrid system compared to the 2.5-D integrated system.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"116-122"},"PeriodicalIF":2.7,"publicationDate":"2025-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11192509","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145352214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reference-Load Sharing Scheme: An Area- and Energy-Efficient Nonvolatile Register Design Using MTJ Devices","authors":"Masanori Natsui;Tomoo Yoshida;Takahiro Hanyu","doi":"10.1109/JXCDC.2025.3611365","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3611365","url":null,"abstract":"This article proposes a circuit configuration for an area- and energy-efficient nonvolatile register using magnetic tunnel junction (MTJ) devices, suitable for persistent computation in intermittent computing environments. The proposed configuration, named the reference-load sharing scheme (RLSS), stores 1 bit of information using the resistance of a dedicated MTJ device and a composite resistance formed by multiple MTJ devices, which serves as a shared reference resistance across all bits. This configuration reduces both the total number of MTJ devices and the energy consumption required for data retention while also decreasing the circuit area through simplifying the write current control circuitry. Functional simulations using a 55-nm CMOS/MTJ-hybrid process technology confirm the advantage of the RLSS across 4-, 8-, 16-, and 32-bit registers. Furthermore, post-layout simulations quantitatively demonstrate that the proposed configuration reduces the backup energy by up to 47.8% and circuit area by up to 38.1% compared to conventional designs.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"90-98"},"PeriodicalIF":2.7,"publicationDate":"2025-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11172316","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145210104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FIMA: A Scalable Ferroelectric Compute-in-Memory Annealer for Accelerating Boolean Satisfiability","authors":"Mohammad Khairul Bashar;T. H. Pantha;Z. Li;M. Farasat;S. Datta;V. Narayanan;S. Dutta;N. Shukla","doi":"10.1109/JXCDC.2025.3603942","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3603942","url":null,"abstract":"In-memory compute kernels present a promising approach for addressing data-centric workloads. However, their scalability—particularly for computationally intensive tasks solving combinatorial optimization problems such as Boolean satisfiability (SAT), which are inherently difficult to decompose—remains a significant challenge. In this work, we propose a ferroelectric nonvolatile memory (NVM)-based compute-in-memory annealer for solving the Boolean MaxSAT problem. We experimentally demonstrate the computational functionality of the NVM array using a compact <inline-formula> <tex-math>$20 times 10$ </tex-math></inline-formula> HZO-/IWO-based ferroelectric field-effect-transistor (FeFET) array. More importantly, through experimentally calibrated simulations, we demonstrate that our solution is compatible with a modular memory architecture, allowing the problem sizes to exceed the capacity of a single memory array. Our approach not only addresses the size limitations imposed by the read margin (RM) of individual arrays but also opens new avenues for integrating such accelerators as back-end solutions in advanced computing platforms.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"81-89"},"PeriodicalIF":2.7,"publicationDate":"2025-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11143213","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145028013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Polar-Axis Orientation Fluctuations and the Impact on the Intrinsic Variability in Ferroelectric Capacitors","authors":"Wei Zhang;Jianze Wang;Xuanyao Fong","doi":"10.1109/JXCDC.2025.3586589","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3586589","url":null,"abstract":"We utilized phase-field simulations to investigate the effects of polar-axis (PA) orientation fluctuations on the extrinsic properties of single ferroelectric (FE) grains, focusing on the coercive electrical field (EC) and the remnant polarization (Pr). The underlying mechanisms through which PA orientation fluctuations influence polarization behavior are studied to gain insights into variations in FE device performance and reliability. In addition, we used the Voronoi algorithm to simulate multigrain (MG) FE capacitors and assess the impact of PA orientation fluctuations on the device variability of polycrystalline FE capacitors. Our analysis shows that the PA orientation, which is a significant intrinsic factor, collectively contributes to device variability. We conclude that engineering the PA orientation helps to optimize FE device performance and reliability, which is crucial for the development of high-performance FE memory technologies.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"74-80"},"PeriodicalIF":2.0,"publicationDate":"2025-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11072438","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144680903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reconfigurable Ferroelectric Bandpass Filter With Low-Frequency Noise Analysis for Intracardiac Electrogram Monitoring","authors":"Jianwei Jia;Zhenge Jia;Omkar Phadke;Yiyu Shi;Shimeng Yu","doi":"10.1109/JXCDC.2025.3584711","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3584711","url":null,"abstract":"Implantable cardioverter defibrillators (ICDs) provide real-time monitoring and immediate defibrillation for life-threatening arrhythmias. However, the intracardiac electrogram (IEGM) acquisition of ICDs faces stringent constraints, including power consumption, low-frequency noise, and patient-specific physiological variability. This article introduces an ultralow-power, high-resolution, reconfigurable three-stage bandpass filter designed specifically for IEGM, utilizing ferroelectric field-effect transistor (FeFET) technology provided by a foundry platform. By employing adjustable threshold voltage <inline-formula> <tex-math>$V {_{text {th}}}$ </tex-math></inline-formula> and gate capacitance of FeFET as programmable pseudo-high-value resistors (PHVRs) and capacitor structures, the filter enables personalized cardiac signal isolation tailored to individual patient needs. In addition, this work incorporates, for the first time, a comprehensive low-frequency noise model covering the entire operational region of FeFET into circuit-level analysis. Based on GlobalFoundries (GF) 28-nm SLPe FeFET-enabled process, the proposed filter achieves a wide gain tuning range (17–77 dB) and a flexible bandwidth tuning range (0.5–19 Hz for low cutoff frequency and 23–138 Hz for high cutoff frequency), with an average power consumption of 257 nW and minimum 11-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>V resolution.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"67-73"},"PeriodicalIF":2.0,"publicationDate":"2025-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11059896","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144606362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Investigation of Minimum Supply Voltage of 5-nm SRAM From 300 K Down to 10 K","authors":"Hafeez Raza;Shivendra Singh Parihar;Yogesh Singh Chauhan;Hussam Amrouch;Avinash Lahgere","doi":"10.1109/JXCDC.2025.3560215","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3560215","url":null,"abstract":"In this article, we present a comprehensive study of the impact of cryogenic temperatures on the minimum operating voltage (<inline-formula> <tex-math>$V_{min }$ </tex-math></inline-formula>) of 5-nm Fin Field-Effect Transistors (FinFETs)-based Static Random Access Memory (SRAM) cells. To perform the SRAM <inline-formula> <tex-math>$V_{min }$ </tex-math></inline-formula> evaluation, we have measured the FinFETs fabricated using a commercial 5-nm technology down to 10 K. Next, we calibrate a cryogenic-aware BSIM-CMG FinFET compact model, which we use with our SRAM evaluation framework. For a comprehensive study, we evaluate three industry-standard SRAM cell types: 1) high-density cell (HDC); 2) low-voltage cell (LVC); and 3) high-performance cell (HPC). We analyze the impact of the threshold voltage (<inline-formula> <tex-math>$V_{text {TH}}$ </tex-math></inline-formula>) and gate length (<inline-formula> <tex-math>$L_{G}$ </tex-math></inline-formula>)-only variations on the SRAM noise resilience. At cryogenic temperature, minimum read voltage (<inline-formula> <tex-math>$V_{min ,R}$ </tex-math></inline-formula>) =0.15 V (62% decrease from room temperature) and minimum write voltage (<inline-formula> <tex-math>$V_{min ,W}$ </tex-math></inline-formula>) =0.45 V are achieved without read-/write-assist circuits. We also highlight that the LVC provides the best tradeoff for <inline-formula> <tex-math>$V_{min }$ </tex-math></inline-formula> between read and write operations for low-power cryogenic applications.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"42-50"},"PeriodicalIF":2.0,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10963695","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143925318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Passive and Scalable High-Order Neuromorphic Circuit Enabled by Mott Memristors","authors":"Zikang Lin;Xiaohui Wu;Shujing Zhao;Weihua Liu;Xin Li;Li Geng;Chuanyu Han","doi":"10.1109/JXCDC.2025.3573709","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3573709","url":null,"abstract":"In this study, VO2 Mott memristors have been successfully fabricated, leading to the proposal of a passive and scalable high-order neural circuit. This circuit consists of two coupled VO2 Mott memristors, two resistors, and three capacitors. The proposed high-order neural circuit demonstrates 11 distinct firing behaviors similar to those of biological neurons, along with controllable burst firing patterns. The spikes, interspike interval (ISI) within a burst, and the quiescence interval between bursts can be adjusted by varying the capacitance and resistance values. In addition, this circuit operates without the need for a bias supply or inductors, enhancing its scalability. This design not only improves circuit interconnection but also effectively reduces power consumption, providing a solid foundation for the development of spiking neural networks (SNNs).","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"60-66"},"PeriodicalIF":2.0,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11015876","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CFET Beyond 3 nm: SRAM Reliability Under Design-Time and Run-Time Variability","authors":"Sufia Shahin;Swati Deshwal;Anirban Kar;Mahdi Benkhelifa;Yogesh S. Chauhan;Hussam Amrouch","doi":"10.1109/JXCDC.2025.3568622","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3568622","url":null,"abstract":"This work investigates the reliability of complementary field-effect transistors (CFETs) by addressing both design-time variability arising from process variations and run-time variability due to temperature and aging effects. A rigorously calibrated TCAD model, validated against experimental CFET data, is employed to quantify the impact of metal gate granularity (MGG)-induced work-function variation (WFV) and random dopant fluctuation (RDF) on key device parameters, including the threshold voltage (<inline-formula> <tex-math>$V_{mathrm {TH}}$ </tex-math></inline-formula>), <sc>on</small>-state current (<inline-formula> <tex-math>$I_{mathrm {ON}}$ </tex-math></inline-formula>), and <sc>off</small>-state current (<inline-formula> <tex-math>$I_{mathrm {OFF}}$ </tex-math></inline-formula>). Temperature-dependent variability is systematically analyzed to further elucidate the behavior of these advanced devices. To capture the dynamic effects of aging, the reaction-diffusion (RD) framework—which accounts for defect generation due to negative bias temperature instability (NBTI)—is implemented in TCAD, enabling detailed modeling of trap generation and the corresponding <inline-formula> <tex-math>$V_{mathrm {TH}}$ </tex-math></inline-formula> shifts in p-type transistors under varying gate stress biases (<inline-formula> <tex-math>$V_{mathrm {GSTR}}$ </tex-math></inline-formula>) and operating temperatures. At the circuit level, a full array of 6T-static random access memory (SRAM) cells with the requisite peripheral circuits is simulated using SPICE after careful calibration of the industry-standard compact model of gate-all-around (BSIM-CMG) against the TCAD data. The variability analysis reveals that the access disturb margin achieves a cell sigma (<inline-formula> <tex-math>$mu /sigma $ </tex-math></inline-formula>) of 17.4 at nominal supply voltage, significantly exceeding the <inline-formula> <tex-math>$6sigma $ </tex-math></inline-formula> robustness criterion for read disturbances. Moreover, as the operating temperature increases from 300 to 398 K, the read static noise margin (RSNM) and hold static noise margin (HSNM) degrade by 13.7% and 6.37%, respectively, while the write static noise margin (WSNM) improves by 18.3%. These findings provide critical insights into the design tradeoffs and reliability challenges of CFET-based SRAMs.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"51-59"},"PeriodicalIF":2.0,"publicationDate":"2025-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10994809","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}