亚 1-V 1T1C FeRAM 存储器电路的设计考虑因素

IF 2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Mohammad Adnaan;Sou-Chi Chang;Hai Li;Yu-Ching Liao;Ian A. Young;Azad Naeemi
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引用次数: 0

摘要

我们为一个晶体管一个电容器(1T1C)低压铁电随机存取存储器(FeRAM)电路提出了一个全面的基准测试框架。我们重点研究了最有前途的铁电材料--氧化锆铪(HZO)和钛酸钡(BTO),它们以快速开关速度和低矫顽力电压而著称。我们利用基于物理的相场模型对铁电电容器进行建模,并根据实验数据对极化开关速度和磁滞环进行校准。我们使用 28 纳米工艺设计工具包 (PDK) 设计了铁电存储器单元,其中包含外围电路和互连寄生。我们建立了存储器阵列电路设计,并通过改变存储器阵列的行/列尺寸以及驱动器和电容器尺寸来分析其性能。在读写延迟和能耗方面,我们将结果与其他新兴存储器技术(尤其是磁性/闪存)进行了比较。我们确定了铁电存储器阵列性能的关键方面,例如压线驱动器和位线电容的影响,并提出了进一步优化此类低工作电压铁电存储器电路性能的建议。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design Considerations for Sub-1-V 1T1C FeRAM Memory Circuits
We present a comprehensive benchmarking framework for one transistor-one capacitor (1T1C) low-voltage ferroelectric random access memory (FeRAM) circuits. We focus on the most promising ferroelectric materials, hafnium zirconium oxide (HZO) and barium titanate (BTO), known for their fast switching speeds and low coercive voltages. We model ferroelectric capacitors using physics-based phase-field models and calibrate the polarization switching speed and hysteresis loop versus experimental data. Ferroelectric memory cells are designed using a 28-nm process design kit (PDK), incorporating peripheral circuitry and interconnect parasitics. We set up the memory array circuit design and analyze its performance by varying the row/column size of the memory array, as well as driver and capacitor sizes. Our results are compared with other emerging memory technologies, particularly magnetic/spintronic memories, in terms of read/write latencies and energy consumption. We identify the critical aspects of the ferroelectric memory array performance, such as the effect of plateline driver and bitline capacitances, and provide recommendations to further optimize the performance of such low operating voltage ferroelectric memory circuits.
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来源期刊
CiteScore
5.00
自引率
4.20%
发文量
11
审稿时长
13 weeks
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