Scaling Logic Area With Multitier Standard Cells

IF 2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Florian Freye;Christian Lanius;Hossein Hashemi Shadmehri;Diana Göhringer;Tobias Gemmeke
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引用次数: 0

Abstract

While the footprint of digital complementary metal-oxide–semiconductor (CMOS) circuits has continued to decrease over the years, physical limitations for further intralayer geometric scaling become apparent. To further increase the logic density, the international roadmap for devices and systems (IRDS) predicts a transition from a single layer of transistors per die to monolithically stacking transistors in multiple tiers starting in 2031. This raises the question of the extent to which these can be exploited in 3-D standard cells to improve logic density. In this work, we investigate the scaling potential of realizing standard cells employing two or three dedicated tiers. For this, specific multitier virtual physical design kits are derived based on the open ASAP7. A typical RISC-V implementation realized in a classic standard cell library is used to identify the subset of the most relevant standard cells. In accordance with the virtual physical design kit (PDK), 3-D derivatives of the single-tier standard cells are crafted and evaluated with respect to achievable logic density considering standard synthesis benchmarks and blocks on the architecture level.
利用多层标准单元扩展逻辑区域
多年来,数字互补金属氧化物半导体(CMOS)电路的占地面积不断缩小,但进一步扩大层内几何尺寸的物理限制也变得显而易见。为了进一步提高逻辑密度,国际器件与系统路线图(IRDS)预测,从 2031 年开始,每个芯片将从单层晶体管过渡到多层晶体管的单片堆叠。这就提出了一个问题:在三维标准单元中可以在多大程度上利用这些晶体管来提高逻辑密度。在这项工作中,我们研究了实现采用两层或三层专用层的标准单元的扩展潜力。为此,我们在开放式 ASAP7 的基础上开发了特定的多层虚拟物理设计工具包。在经典标准单元库中实现的典型 RISC-V 实现用于确定最相关的标准单元子集。根据虚拟物理设计工具包 (PDK),制作了单层标准单元的三维衍生物,并根据可实现的逻辑密度(考虑标准综合基准和架构级模块)进行了评估。
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来源期刊
CiteScore
5.00
自引率
4.20%
发文量
11
审稿时长
13 weeks
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