Energy-/Carbon-Aware Evaluation and Optimization of 3-D IC Architecture With Digital Compute-in-Memory Designs

IF 2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Hyung Joon Byun;Udit Gupta;Jae-Sun Seo
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引用次数: 0

Abstract

Several 2-D architectures have been presented, including systolic arrays or compute-in-memory (CIM) arrays for energy-efficient artificial intelligence (AI) inference. To increase the energy efficiency within constrained area, 3-D technologies have been actively investigated, which have the potential to decrease the data path length or increase the activation buffer size, enabling higher energy efficiency. Several works have reported the 3-D architectures using non-CIM designs, but investigations on 3-D architectures with CIM macros have not been well studied in prior works. In this article, we investigate digital CIM (DCIM) macros and various 3-D architectures to find the opportunity of increased energy efficiency compared with 2-D structures. Moreover, we also investigated the carbon footprint of 3-D architectures. We have built in-house simulators calculating energy and area given high-level hardware descriptions and DNN workloads and integrated with carbon estimation tool to analyze the embodied carbon of various hardware designs. We have investigated different types of 3-D DCIM architectures and dataflows, which have shown 42.5% energy savings compared with 2-D systolic arrays on average. Also, we have analyzed the tradeoff between performance and carbon footprint and their optimization opportunities.
采用数字内存计算设计的三维集成电路架构的能源/碳意识评估与优化
目前已经提出了几种二维架构,包括用于高能效人工智能(AI)推理的收缩阵列或内存计算(CIM)阵列。为了在有限的面积内提高能效,人们积极研究三维技术,这些技术有可能减少数据路径长度或增加激活缓冲区大小,从而实现更高的能效。有几篇文章报道了使用非 CIM 设计的三维架构,但之前的文章对使用 CIM 宏的三维架构研究不多。在本文中,我们研究了数字 CIM(DCIM)宏和各种三维架构,以寻找与二维结构相比提高能效的机会。此外,我们还研究了三维结构的碳足迹。我们建立了内部模拟器,根据高级硬件描述和 DNN 工作负载计算能量和面积,并与碳估算工具集成,以分析各种硬件设计的含碳量。我们研究了不同类型的三维 DCIM 架构和数据流,结果表明,与二维收缩阵列相比,平均节能 42.5%。此外,我们还分析了性能与碳足迹之间的权衡及其优化机会。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
CiteScore
5.00
自引率
4.20%
发文量
11
审稿时长
13 weeks
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