Reference-Load Sharing Scheme: An Area- and Energy-Efficient Nonvolatile Register Design Using MTJ Devices

This article proposes a circuit configuration for an area- and energy-efficient nonvolatile register using magnetic tunnel junction (MTJ) devices, suitable for persistent computation in intermittent computing environments. The proposed configuration, named the reference-load sharing scheme (RLSS), stores 1 bit of information using the resistance of a dedicated MTJ device and a composite resistance formed by multiple MTJ devices, which serves as a shared reference resistance across all bits. This configuration reduces both the total number of MTJ devices and the energy consumption required for data retention while also decreasing the circuit area through simplifying the write current control circuitry. Functional simulations using a 55-nm CMOS/MTJ-hybrid process technology confirm the advantage of the RLSS across 4-, 8-, 16-, and 32-bit registers. Furthermore, post-layout simulations quantitatively demonstrate that the proposed configuration reduces the backup energy by up to 47.8% and circuit area by up to 38.1% compared to conventional designs.