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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits publication information 探索性固态计算器件和电路IEEE杂志出版信息
IF 2.4
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-01 DOI: 10.1109/JXCDC.2022.3231737
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引用次数: 0
SSRL: Single Skyrmion Reconfigurable Logic Utilizing 2-D Magnus Force on Magnetic Racetracks SSRL:在磁性赛道上利用二维磁力的单个Skyrmion可重构逻辑
IF 2.4
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-01 DOI: 10.1109/JXCDC.2023.3238030
Mohammad Nazmus Sakib;Hamed Vakili;Samiran Ganguly;Avik W. Ghosh;Mircea Stan
{"title":"SSRL: Single Skyrmion Reconfigurable Logic Utilizing 2-D Magnus Force on Magnetic Racetracks","authors":"Mohammad Nazmus Sakib;Hamed Vakili;Samiran Ganguly;Avik W. Ghosh;Mircea Stan","doi":"10.1109/JXCDC.2023.3238030","DOIUrl":"10.1109/JXCDC.2023.3238030","url":null,"abstract":"Magnetic racetrack memory has frequently been complicated by the pinning of domain wall bits on the one hand and the need to engineer precise synchronization and inter-track repulsion between skyrmionic bits on the other. Such proposals, however, do not capitalize on the complex 2-D motion of skyrmions, such as transverse Magnus force that tends to deviate the skyrmion trajectory from rectilinear motion along the current drive. The transverse deviation associated with such a skyrmion Hall effect is normally considered a liability for skyrmions, and efforts have focused on eliminating rather than utilizing it for proposed device applications. We propose a simple single skyrmion-based circuit macro with elementary and higher-order logic gates that utilize Magnus force and propose reconfigurable logic built on these gates. We demonstrate the reliability of the proposed approach with micromagnetics simulation. The energy consumption in this circuit lies mainly in the overhead, with the racetrack consuming a small fraction. The energy–delay product (EDP) is correspondingly low and can be improved by boosting the skyrmion speed.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9998452/10021607.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41852686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Special Topic on Energy-Efficient Compute-in-Memory With Emerging Devices 专题:新兴设备的节能内存计算
IF 2.4
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-01 DOI: 10.1109/JXCDC.2022.3231764
Jae-Sun Seo
{"title":"Special Topic on Energy-Efficient Compute-in-Memory With Emerging Devices","authors":"Jae-Sun Seo","doi":"10.1109/JXCDC.2022.3231764","DOIUrl":"https://doi.org/10.1109/JXCDC.2022.3231764","url":null,"abstract":"Deep neural networks (DNNs) have shown extraordinary performance in recent years for various applications including image classification, object detection, speech recognition, natural language processing, etc. Accuracydriven DNN architectures tend to increase the model sizes and computations at a very fast pace, demanding a massive amount of hardware resources. Frequent communication between the processing engine and the ON-/OFF-chip memory leads to high energy consumption, which becomes a bottleneck for the conventional DNN accelerator design.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9969523/10006410.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49978852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
RFIC 2023 Call for Papers RFIC 2023征稿
IF 2.4
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-01 DOI: 10.1109/JXCDC.2022.3218810
{"title":"RFIC 2023 Call for Papers","authors":"","doi":"10.1109/JXCDC.2022.3218810","DOIUrl":"https://doi.org/10.1109/JXCDC.2022.3218810","url":null,"abstract":"","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9969523/10102698.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49950212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
2022 Index IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Vol. 8 探索性固态计算器件和电路IEEE杂志第8卷
IF 2.4
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-01 DOI: 10.1109/JXCDC.2023.3268019
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引用次数: 0
Special Topic on Spintronic Devices for Energy-Efficient Computing 用于节能计算的自旋电子器件专题
IF 2.4
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-01 DOI: 10.1109/JXCDC.2023.3264859
Jian-Ping Wang
{"title":"Special Topic on Spintronic Devices for Energy-Efficient Computing","authors":"Jian-Ping Wang","doi":"10.1109/JXCDC.2023.3264859","DOIUrl":"10.1109/JXCDC.2023.3264859","url":null,"abstract":"The traditional scaling trend of semiconductor devices is approaching its limit with the node size in manufacturing already down to 2 nm, with a great guidance from Moore’s law. Heterogenous integration has recently been one of the major driving forces to push the semiconductor technologies further, with a great engineering effort to sum up the power of known and established technologies.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9998452/10102339.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49440758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits publication information 探索性固态计算器件和电路IEEE杂志出版信息
IF 2.4
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-01 DOI: 10.1109/JXCDC.2023.3263708
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引用次数: 0
Review of Magnetic Tunnel Junctions for Stochastic Computing 随机计算中磁隧道结的研究进展
IF 2.4
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-01 DOI: 10.1109/JXCDC.2022.3227062
Brandon R. Zink, Yang Lv, Jian‐Ping Wang
{"title":"Review of Magnetic Tunnel Junctions for Stochastic Computing","authors":"Brandon R. Zink, Yang Lv, Jian‐Ping Wang","doi":"10.1109/JXCDC.2022.3227062","DOIUrl":"https://doi.org/10.1109/JXCDC.2022.3227062","url":null,"abstract":"Modern computing schemes require large circuit areas and large energy consumption for neuromorphic computing applications, such as recognition, classification, and prediction. This is because these tasks require parallel processing on large datasets. Stochastic computing (SC) is a promising alternative to conventional binary computing schemes due to its low area cost, low processing power, and robustness to noise. However, the large area and energy costs for random number generation with CMOS-based circuits make SC impractical for most hardware implementations. For this reason, beyond-CMOS approaches to random number generation have been investigated in recent years. Spintronics is one of the most promising approaches due to the intrinsic stochasticity of the magnetic tunnel junction (MTJ). In this review article, we provide an overview of the literature published in recent years investigating the tunable, intrinsic stochasticity of MTJs and proposing practical methods for random number generation using spintronic hardware.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62235055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
INFORMATION FOR AUTHORS 作者信息
IF 2.4
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-12-01 DOI: 10.1109/JXCDC.2023.3263712
{"title":"INFORMATION FOR AUTHORS","authors":"","doi":"10.1109/JXCDC.2023.3263712","DOIUrl":"https://doi.org/10.1109/JXCDC.2023.3263712","url":null,"abstract":"","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9998452/10102689.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49978849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Binarized Neural Network Accelerator Macro Using Ultralow-Voltage Retention SRAM for Energy Minimum-Point Operation 用于能量最小点操作的超低电压保持SRAM二进制化神经网络加速器宏
IF 2.4
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Pub Date : 2022-11-30 DOI: 10.1109/JXCDC.2022.3225744
Yusaku Shiotsu;Satoshi Sugahara
{"title":"Binarized Neural Network Accelerator Macro Using Ultralow-Voltage Retention SRAM for Energy Minimum-Point Operation","authors":"Yusaku Shiotsu;Satoshi Sugahara","doi":"10.1109/JXCDC.2022.3225744","DOIUrl":"10.1109/JXCDC.2022.3225744","url":null,"abstract":"A binarized neural network (BNN) accelerator based on a processing-in-memory (PIM)/ computing-in-memory (CIM) architecture using ultralow-voltage retention static random access memory (ULVR-SRAM) is proposed for the energy minimum-point (EMP) operation. The BNN accelerator (BNA) macro is designed to perform stable inference operations at EMP and substantive power-gating (PG) using ULVR at an ultralow voltage (< EMP), which can be applied to fully connected layers (FCLs) with arbitrary shapes and sizes. The EMP operation of the BNA macro, which is enabled by applying the ULVR-SRAM to the macro, can dramatically improve the energy efficiency (TOPS/W) and significantly enlarge the number of parallelized multiply–accumulate (MAC) operations. In addition, the ULVR mode of the BNA macro, which also benefits from the usage of ULVR-SRAM, is effective at reducing the standby power. The proposed BNA macro can show a high energy efficiency of 65 TOPS/W for FCLs. This BNA macro concept using the ULVR-SRAM can be expanded to convolution layers, where the EMP operation is also expected to enhance the energy efficiency of convolution layers.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":null,"pages":null},"PeriodicalIF":2.4,"publicationDate":"2022-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9969523/09966581.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44044898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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