Iet Circuits Devices & Systems最新文献

{"title":"A CMOS slew-rate controlled output driver with low process, voltage and temperature variations using a dual-path signal-superposition technique","authors":"Xiaoyan Gui,&nbsp;Renjie Tang,&nbsp;Kai Li,&nbsp;Kanan Wang,&nbsp;Dan Li,&nbsp;Quan Pan,&nbsp;Li Geng","doi":"10.1049/cds2.12133","DOIUrl":"https://doi.org/10.1049/cds2.12133","url":null,"abstract":"<p>A dual-path open-loop slew-rate (SR) controlled Complementary Metal Oxide Semiconductor (CMOS) driver is presented in this study. The proposed output driver incorporates a delay-locked loop (DLL) to minimise the SR variations over process, voltage and temperature, generating delayed versions of transmitted signal by sampling the input data with adjacent phases of the clock from the DLL. A dual-path open-loop signal-superposition technique is introduced to suppress the high-frequency components of the output driver and thus improves the SR of the CMOS driver. The proposed CMOS output driver achieves a maximum SR of 1.00 and &lt;0.35 V/ns variation operating at 500 Mbps over 32 corners. Both the conventional CMOS driver and the proposed SR controlled output driver were fabricated in a 0.18 μm CMOS process. The proposed driver occupies a compact area of 0.088 mm² and consumes 55.27 mW with a 1.8 V supply voltage. Measurement results show that the SR of the proposed output driver is &lt;0.816 V/ns, corresponding to 62% reduction compared with that of a conventional output driver, and the total jitter is &lt;0.16 unit interval.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"17 1","pages":"13-28"},"PeriodicalIF":1.3,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12133","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50155920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimised ladder-climbing rehabilitation training for various stroke severity levels in rats","authors":"Chi-Chun Chen,&nbsp;Yu-Lin Wang,&nbsp;Ching-Ping Chang","doi":"10.1049/cds2.12132","DOIUrl":"10.1049/cds2.12132","url":null,"abstract":"<p>To develop an optimised rehabilitation training system for various severity strokes in rats. The method provided feedback regarding the rat's measured position to a microprocessor, which adjusted the training speed accordingly and enables the rat to continuously exercise in the middle position of the ladder. This created a cyclic control system that provided various training intensities based on timely evaluations of the ladder-climbing capabilities of each rat, thus providing a suitable rehabilitation method for subjects with various stroke severities. The modified neurological severity score, rotarod and cerebral infarction volume results for the 60- and 90-min middle cerebral artery occlusion (MCAO) treadmill groups did not differ significantly from those of the control group. Conversely, the cerebral infarction volumes of the ladder-climbing rehabilitation groups in the 30-, 60-, and 90-min MCAO were all significantly lower than those of the control group (84.03 ± 23.24 vs. 256.77 ± 85.63 (mm³), 265.19 ± 41.12 versus 377.17 ± 90.97 (mm³), and 303.80 ± 47.15 versus 452.68 ± 90.44 (mm³) respectively), thereby indicating the optimised ladder-climbing method as effective for subjects with various stroke severities. Individual differences may cause different exercise capacities for each participant. To accommodate for these exercise capacities, an optimised ladder-climbing rehabilitation training system was proposed, which provided training according to the physical abilities of each participant.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 8","pages":"598-610"},"PeriodicalIF":1.3,"publicationDate":"2022-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12132","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128778978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Retracted: Research on tridimensional monitoring and defence technology of substation","authors":"Kaiyi Qiu,&nbsp;Xin Liu,&nbsp;Jie Liu,&nbsp;Hongbo Ma,&nbsp;Jingya Li,&nbsp;Zhengchao Zhang,&nbsp;Guangliang Chen,&nbsp;Li Cai","doi":"10.1049/cds2.12129","DOIUrl":"https://doi.org/10.1049/cds2.12129","url":null,"abstract":"<p>Retraction: [Kaiyi Qiu, Xin Liu, Jie Liu, Hongbo Ma, Jingya Li, Zhengchao Zhang, Guangliang Chen, Li Cai, Research on tridimensional monitoring and defence technology of substation, <i>IET Circuits, Devices &amp; Systems</i> 2022 (https://doi.org/10.1049/cds2.12129)].</p><p>The above article from <i>IET Circuits, Devices &amp; Systems</i>, published online on 14 September 2022 in Wiley Online Library (wileyonlinelibrary.com), has been retracted by agreement between the Editor-in-Chief, Harry E. Ruda, the Institution of Engineering and Technology (the IET) and John Wiley and Sons Ltd. This article was published as part of a Guest Edited special issue. Following an investigation, the IET and the journal have determined that the article was not reviewed in line with the journal’s peer review standards and there is evidence that the peer review process of the special issue underwent systematic manipulation. Accordingly, we cannot vouch for the integrity or reliability of the content. As such we have taken the decision to retract the article. The authors have been informed of the decision to retract.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"17 4","pages":"258-267"},"PeriodicalIF":1.3,"publicationDate":"2022-09-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12129","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50133162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel buffering fault-tolerance approach for network on chip (NoC)","authors":"Nima Jafarzadeh,&nbsp;Ahmad Jalili,&nbsp;Jafar A. Alzubi,&nbsp;Khosro Rezaee,&nbsp;Yang Liu,&nbsp;Mehdi Gheisari,&nbsp;Bahram Sadeghi Bigham,&nbsp;Amir Javadpour","doi":"10.1049/cds2.12127","DOIUrl":"https://doi.org/10.1049/cds2.12127","url":null,"abstract":"<p>Network-on-Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication between many cores. NoC is a network-based communication subsystem on an integrated circuit, most typically between modules in a system on a chip (SoC). Designing a reliable NoC against failures that can prevent failure using some measures or preventing error or system failure while failure happens and proper performance became a significant concern. For a reliable design against failures, first, the system should be analysed to discover the critical points. Hence, in this research, it is tried first to investigate the scale of fault tolerance effect on the mechanism in the router on the network by injecting simulated errors, and then these errors are prevented. As the major novelty, the authors implemented a router on a synchronised network and calculated the network buffering fault tolerance by injecting error in the buffer. Specifically, a new method for improving fault tolerance is proposed, which uses the existing resources efficiently. So, it does not impose any overhead on hardware and improves the error tolerance scale. The authors also evaluate it from different perspectives to show its superior performance.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"17 4","pages":"250-257"},"PeriodicalIF":1.3,"publicationDate":"2022-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12127","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50144119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Challenges and solutions of working under threshold supply-voltage, for CNTFET-based SRAM-bitcell","authors":"Salimeh Shahrabadi","doi":"10.1049/cds2.12126","DOIUrl":"10.1049/cds2.12126","url":null,"abstract":"&lt;p&gt;Recently, several studies were done on SRAM bitcells at different supply-voltages; upper, near or lower to threshold voltage. To the best of the author's knowledge, none of them discussed at threshold supply-voltage with proper subthreshold operations and Nano/Pico power-dissipations, hence this paper decides to investigate challenges and solutions of designing at &lt;math&gt;\u0000 &lt;semantics&gt;\u0000 &lt;mrow&gt;\u0000 &lt;msub&gt;\u0000 &lt;mi&gt;V&lt;/mi&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mi&gt;D&lt;/mi&gt;\u0000 &lt;mi&gt;D&lt;/mi&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;/msub&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;annotation&gt; ${mathbf{V}}_{mathbf{D}mathbf{D}}$&lt;/annotation&gt;\u0000 &lt;/semantics&gt;&lt;/math&gt; =  &lt;math&gt;\u0000 &lt;semantics&gt;\u0000 &lt;mrow&gt;\u0000 &lt;msub&gt;\u0000 &lt;mi&gt;V&lt;/mi&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mi&gt;t&lt;/mi&gt;\u0000 &lt;mi&gt;h&lt;/mi&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;/msub&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;annotation&gt; ${mathbf{V}}_{mathbf{t}mathbf{h}}$&lt;/annotation&gt;\u0000 &lt;/semantics&gt;&lt;/math&gt;, because this voltage will lead to having lower power consumptions. This research applies power-gating technique to adjust &lt;math&gt;\u0000 &lt;semantics&gt;\u0000 &lt;mrow&gt;\u0000 &lt;msub&gt;\u0000 &lt;mi&gt;V&lt;/mi&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mi&gt;D&lt;/mi&gt;\u0000 &lt;mi&gt;D&lt;/mi&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;/msub&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;annotation&gt; ${mathbf{V}}_{mathbf{D}mathbf{D}}$&lt;/annotation&gt;\u0000 &lt;/semantics&gt;&lt;/math&gt; on &lt;math&gt;\u0000 &lt;semantics&gt;\u0000 &lt;mrow&gt;\u0000 &lt;msub&gt;\u0000 &lt;mi&gt;V&lt;/mi&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mi&gt;t&lt;/mi&gt;\u0000 &lt;mi&gt;h&lt;/mi&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;/msub&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;annotation&gt; ${mathbf{V}}_{mathbf{t}mathbf{h}}$&lt;/annotation&gt;\u0000 &lt;/semantics&gt;&lt;/math&gt;, and also utilises output-inverter to set Logic 1 at &lt;math&gt;\u0000 &lt;semantics&gt;\u0000 &lt;mrow&gt;\u0000 &lt;msub&gt;\u0000 &lt;mi&gt;V&lt;/mi&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mi&gt;D&lt;/mi&gt;\u0000 &lt;mi&gt;D&lt;/mi&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;/msub&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;annotation&gt; ${mathbf{V}}_{mathbf{D}mathbf{D}}$&lt;/annotation&gt;\u0000 &lt;/semantics&gt;&lt;/math&gt;. Although ‘power-gating’ and ‘output-inverter’ were used in other works, this study renders specific points about them. In fact, the ability of power-gating technique in adjusting &lt;math&gt;\u0000 &lt;semantics&gt;\u0000 &lt;mrow&gt;\u0000 &lt;msub&gt;\u0000 &lt;mi&gt;V&lt;/","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 8","pages":"569-580"},"PeriodicalIF":1.3,"publicationDate":"2022-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12126","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116679492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and optimisation of high-efficient class-F ULP-PA using envelope tracking supply bias control for long-range low power wireless local area network IEEE 802.11ah standard using 65 nm CMOS technology","authors":"Muhammad Ovais Akhter,&nbsp;Najam Muhammad Amin,&nbsp;Razia Zia","doi":"10.1049/cds2.12125","DOIUrl":"10.1049/cds2.12125","url":null,"abstract":"<p>This article presents the design and optimisation of a sub-1 GHz class-F ultra-low power (ULP) power amplifier (PA) in 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. An envelope tracking (ET) supply biasing technique is adopted to improve the efficiency of class-F PA. The ET consist of a pre-amp right before the detector in order to enhance the efficiency and save adequate amount of dc power consumption. The PA consists of two cascode cells terminated as class-F with gate-to-drain feedback in order to enhance linearity and limit any harmonic component from the input signal. The novel design consumes a dc power of 3.75 mW, power added efficiency of 37.1%, operating at 915–925 MHz unlicensed band and total saturated output power of 22 dBm including 14 dBm power gain at PA, which qualifies under long-range low power wireless local area network IEEE 802.11ah standard. The inductor-less design for ET supply bias reduces the chip layout size to 0.13 mm² only.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 7","pages":"553-568"},"PeriodicalIF":1.3,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12125","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121511855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Methods of solving in-band ripples and out-of-band suppression for yarn tension sensor based on surface acoustic wave","authors":"Yang Feng,&nbsp;Jun Li,&nbsp;Ru Bai,&nbsp;Zhenghong Qian","doi":"10.1049/cds2.12121","DOIUrl":"10.1049/cds2.12121","url":null,"abstract":"<p>The two key problems of the in-band ripples and out-of-band suppression are proposed in the design of the SAW yarn tension sensor and the methods of decreasing them are achieved. The unbalanced split-electrode interdigital transducers (IDT) are designed so that the total phase of the regenerated reflection wave and mass load feedback is close to 180°, leading to an effective reduction of the in-band ripples effect characterised by the sensor frequency response. The engraved bi-directional slots on the back of the substrate can block the propagation path of the bulk acoustic wave (BAW) to a certain extent, reducing the influence of BAW propagation and suppressing the out-of-band suppression of the frequency response. The experimental results show that the SAW yarn tension sensor with the unbalanced split-electrode IDT can reduce the in-band ripples from 23.34 to 0.93 dB, and the engraved bi-directional slots can suppress the out-of-band suppression from 28.03 to 7.71 dB.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 6","pages":"483-490"},"PeriodicalIF":1.3,"publicationDate":"2022-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12121","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131288564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 1–5 GHz 22 mW receiver frontend with active-feedback baseband and voltage-commutating mixers in 65 nm CMOS","authors":"Benqing Guo,&nbsp;Haishi Wang,&nbsp;Huifen Wang,&nbsp;Lei Li,&nbsp;Wanting Zhou,&nbsp;Kianoosh Jalali","doi":"10.1049/cds2.12124","DOIUrl":"10.1049/cds2.12124","url":null,"abstract":"<p>A CMOS baseband-active-feedback receiver frontend with passive voltage-commutating mixers is proposed. The active feedback baseband enables in-band signal amplification and out-of-band blocker interference suppression by constructing the RF bandpass filter and BB lowpass filter, simultaneously. The voltage-commutating mixers embedded in current mirrors significantly reduce the power requirement for the LO generator. The stacked n/pMOS structure is commonly adopted to further improve power efficiency. The receiver frontend is designed in a standard 65 nm CMOS process. Simulation results display an NF of 3.4 dB and a maximum gain of 32 dB from 1 to 5 GHz LO frequency range. The obtained in-band and out-of-band IIP3 are −12 dBm and 9 dBm, respectively. The receiver frontend core only consumes 22 mW at 1 GHz LO frequency and occupies the area of 645 × 543 μm², which is suitable for the low-power application of handheld terminals.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 7","pages":"543-552"},"PeriodicalIF":1.3,"publicationDate":"2022-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12124","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130189731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 5.5–7.5-GHz band-configurable wake-up receiver fully integrated in 45-nm RF-SOI CMOS","authors":"Rui Ma,&nbsp;Florian Protze,&nbsp;Frank Ellinger","doi":"10.1049/cds2.12123","DOIUrl":"10.1049/cds2.12123","url":null,"abstract":"<p>This work investigates a 5.5–7.5-GHz band-configurable duty-cycled wake-up receiver (WuRX) fully implemented in a 45-nm radio-frequency (RF) silicon-on-insulator (SOI) complementary-metal-oxide-semiconductor (CMOS) technology. Based on an uncertain intermediate frequency (IF) super-heterodyne receiver (RX) topology, the WuRX analogue front-end (AFE) incorporates a 5.5–7.5-GHz band-tunable low-power low-noise amplifier, a low-power Gilbert mixer, a digitally controlled oscillator (DCO), a 100-MHz IF band-pass filter (BPF), an envelope detector, a comparator, a pulse generator and a current reference. By application of duty cycling with a low duty cycle below 1%, the power consumption of the AFE was significantly reduced. In addition, the on-chip digital bank-end consists of a frequency divider, a phase corrector, a 31-bit correlator and a serial peripheral interface. A proof-of-concept WuRX circuit occupying an area of 1200 <i>μ</i>m by 900 <i>μ</i>m has been fabricated in a GlobalFoundries 45-nm RF-SOI CMOS technology. Measurement results show that at a data rate of 64 bps, the entire WuRX consumes only 2.3 <i>μ</i>W. Tested at 8 operation bands covering 5.5–7.7 GHz, the WuRX has a measured sensitivity between −67.5 dBm and −72.4 dBm at a wake-up error rate of 10⁻³. With the sensitivity unchanged, the data rate of the WuRX can be scaled up to 8.2 kbps. To the authors' best knowledge, this work offers the largest RF bandwidth from 5.5 to 7.5 GHz, the most operation channels (≥8) and the fastest settling time (&lt;115 ns) among the WuRXs reported to date.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 7","pages":"525-542"},"PeriodicalIF":1.3,"publicationDate":"2022-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12123","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116842801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of a multi-mode digital pixel with conversion data protection","authors":"Yan-Hua Ma,&nbsp;Xiang-He Kong,&nbsp;Yu-Chun Chang","doi":"10.1049/cds2.12122","DOIUrl":"10.1049/cds2.12122","url":null,"abstract":"<p>With the development of semiconductor technology, digital pixel has received widespread attention and is applied to various electronic products. However, due to the limitation of area, it forms a challenging task to design a digital pixel with multiple modes. In this paper, a pulse width modulation based digital pixel is proposed, which is compatible with five different modes. By using the multi-purpose capacitors and static random access memory structure, it can realise multi-mode conversion in an equivalent area to that of the single mode digital pixel without performance degradation. Furthermore, a corresponding logic control method is developed, such that the integrity of the frame data is ensured during mode conversion. The simulation result of our proposed digital pixel in Tower Jazz 0.18 μm process shows that in the bright field it achieves a dynamic range of 67 dB. In the dark field, it achieves a conversion gain up to 13.91 μV/e−, with input noise of 37.89 e−per pixel after correlated double sampling.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 7","pages":"501-524"},"PeriodicalIF":1.3,"publicationDate":"2022-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12122","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130907035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}