Iet Circuits Devices & Systems最新文献_第6页

A 1–5 GHz 22 mW receiver frontend with active-feedback baseband and voltage-commutating mixers in 65 nm CMOS 1 - 5ghz 22mw接收器前端，主动反馈基带和电压换流混频器，65nm CMOS

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2022-06-15 DOI: 10.1049/cds2.12124

Benqing Guo, Haishi Wang, Huifen Wang, Lei Li, Wanting Zhou, Kianoosh Jalali

引用次数: 6

A 5.5–7.5-GHz band-configurable wake-up receiver fully integrated in 45-nm RF-SOI CMOS 5.5 - 7.5 ghz波段可配置唤醒接收器，完全集成在45nm RF-SOI CMOS中

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2022-06-09 DOI: 10.1049/cds2.12123

Rui Ma, Florian Protze, Frank Ellinger

{"title":"A 5.5–7.5-GHz band-configurable wake-up receiver fully integrated in 45-nm RF-SOI CMOS","authors":"Rui Ma, Florian Protze, Frank Ellinger","doi":"10.1049/cds2.12123","DOIUrl":"10.1049/cds2.12123","url":null,"abstract":"This work investigates a 5.5–7.5-GHz band-configurable duty-cycled wake-up receiver (WuRX) fully implemented in a 45-nm radio-frequency (RF) silicon-on-insulator (SOI) complementary-metal-oxide-semiconductor (CMOS) technology. Based on an uncertain intermediate frequency (IF) super-heterodyne receiver (RX) topology, the WuRX analogue front-end (AFE) incorporates a 5.5–7.5-GHz band-tunable low-power low-noise amplifier, a low-power Gilbert mixer, a digitally controlled oscillator (DCO), a 100-MHz IF band-pass filter (BPF), an envelope detector, a comparator, a pulse generator and a current reference. By application of duty cycling with a low duty cycle below 1%, the power consumption of the AFE was significantly reduced. In addition, the on-chip digital bank-end consists of a frequency divider, a phase corrector, a 31-bit correlator and a serial peripheral interface. A proof-of-concept WuRX circuit occupying an area of 1200 μm by 900 μm has been fabricated in a GlobalFoundries 45-nm RF-SOI CMOS technology. Measurement results show that at a data rate of 64 bps, the entire WuRX consumes only 2.3 μW. Tested at 8 operation bands covering 5.5–7.7 GHz, the WuRX has a measured sensitivity between −67.5 dBm and −72.4 dBm at a wake-up error rate of 10−3. With the sensitivity unchanged, the data rate of the WuRX can be scaled up to 8.2 kbps. To the authors' best knowledge, this work offers the largest RF bandwidth from 5.5 to 7.5 GHz, the most operation channels (≥8) and the fastest settling time (<115 ns) among the WuRXs reported to date.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2022-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12123","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116842801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of a multi-mode digital pixel with conversion data protection 带转换数据保护的多模数字像素的设计

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2022-06-07 DOI: 10.1049/cds2.12122

Yan-Hua Ma, Xiang-He Kong, Yu-Chun Chang

引用次数: 0

A novel design of a silicon PIN diode for increasing the breakdown voltage 一种提高击穿电压的新型硅PIN二极管设计

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2022-06-06 DOI: 10.1049/cds2.12120

Farzaneh Rezaei, Fatemeh Dehghan Nayeri, Adel Rezaeian

引用次数: 1

Bipartite consensus in coupled harmonic oscillators with local instantaneous interaction and measurement noise 局部瞬时相互作用和测量噪声耦合谐振子的二部一致性

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2022-05-06 DOI: 10.1049/cds2.12118

Zhaoyan Wang, Hengyu Li, Jun Liu, Tiehui Zhang, Xinru Ma, Shaorong Xie, Jun Luo

引用次数: 0

Calculated characterisation of a sensitive gas sensor based on PEDOT:PSS 基于PEDOT:PSS的灵敏气体传感器的计算特性

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2022-04-30 DOI: 10.1049/cds2.12119

Mokhtar Aarabi, Alireza Salehi, Alireza Kashaninia

引用次数: 0

Tolerant and low power subtractor with 4:2 compressor and a new TG-PTL-float full adder cell 容忍和低功耗减法器与4:2压缩机和一个新的tg - ptl浮动全加法器单元

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2022-04-25 DOI: 10.1049/cds2.12117

Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee, Rahim Ghayour

{"title":"Tolerant and low power subtractor with 4:2 compressor and a new TG-PTL-float full adder cell","authors":"Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee, Rahim Ghayour","doi":"10.1049/cds2.12117","DOIUrl":"10.1049/cds2.12117","url":null,"abstract":"A new 1-bit full adder (FA) cell illustrating low-power, high-speed, and a small area is presented by a combination of transmission gate (TG), pass transistor logic (PTL), and float techniques. Using the proposed cell, a 4:2 compressor is implemented and its performance is investigated under diverse circumstances of voltage, temperature, and driving. The process and corners are evaluated through the process-voltage-temperature (PVT) variations and the Monte Carlo method (MCM), respectively. The accuracy and reliability of the proposed 4:2 compressor are confirmed carefully. Utilising the proposed FA and the compressor, an efficient 8-bit subtractor is implemented for bioimage processing, in particular for difference detection of images. A new mechanism is presented to improve the detection performance of digital signal processors (DSPs) by the addition and subtraction of two images for their difference. The quality of the resulted image confirms the efficiency of the proposed circuits and the method. The high performance of the circuits makes them a promising candidate for the next generation of integrated circuits (ICs) applicable to medical image processing.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2022-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12117","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124149929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A high-performance processor for optimal ate pairing computation over Barreto–Naehrig curves Barreto-Naehrig曲线最优共轭计算的高性能处理器

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2022-04-06 DOI: 10.1049/cds2.12116

Yujun Xie, Bin Wang, Lijun Zhang, Xin Zheng, Xiaoling Lin, Xiaoming Xiong, Yuan Liu

{"title":"A high-performance processor for optimal ate pairing computation over Barreto–Naehrig curves","authors":"Yujun Xie, Bin Wang, Lijun Zhang, Xin Zheng, Xiaoling Lin, Xiaoming Xiong, Yuan Liu","doi":"10.1049/cds2.12116","DOIUrl":"10.1049/cds2.12116","url":null,"abstract":"This paper presents a high-performance processor for optimal ate pairing on Barreto–Naehrig curves over 256-bit prime field at the 128-bit security level. The proposed design exploits parallelism and pipeline at different levels of the pairing algorithm, including the prime field operation, the second extension of the prime field <math>\u0000 <semantics>\u0000 <mrow>\u0000 <mfenced>\u0000 <msub>\u0000 <mi>F</mi>\u0000 <msup>\u0000 <mi>p</mi>\u0000 <mn>2</mn>\u0000 </msup>\u0000 </msub>\u0000 </mfenced>\u0000 </mrow>\u0000 <annotation> $left({F}_{{p}^{2}}right)$</annotation>\u0000 </semantics></math> operation, and operations based on <math>\u0000 <semantics>\u0000 <mrow>\u0000 <msub>\u0000 <mi>F</mi>\u0000 <msup>\u0000 <mi>p</mi>\u0000 <mn>2</mn>\u0000 </msup>\u0000 </msub>\u0000 </mrow>\u0000 <annotation> ${F}_{{p}^{2}}$</annotation>\u0000 </semantics></math>. The proposed design needs 37,271 cycles to compute optimal ate pairings. The results of implementation on a 90 nm standard cell library show that the proposed design consumes 751k gates and can compute the respective pairings in 0.10 ms. This result is at least 60 percent better than related reports in terms of normalised area-time on ASIC. Moreover, the design is also implemented on Xilinx Virtex-6 platform, which consumes 25K Slices and 240 DSPs and takes 0.52 ms to calculate one optimal ate pairing operation.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12116","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128482462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

1.2 kV 4H-SiC planar power MOSFETs with a low-K dielectric in central gate 1.2 kV低k介电介质中央栅极4H-SiC平面功率mosfet

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2022-03-30 DOI: 10.1049/cds2.12115

Dong Liu, Mingyue Li, Yangjie Ou, Zhong Lan, Maosen Tang, Weibo Wang, Xiarong Hu

引用次数: 1

Onto a higher power handling for very high frequency direct antenna modulation 到一个更高的功率处理非常高的频率直接天线调制

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2022-03-17 DOI: 10.1049/cds2.12108

Jean Paul D. Santos, Kamal Bhakta, Foad Fereidoony, Yuanxun Ethan Wang

{"title":"Onto a higher power handling for very high frequency direct antenna modulation","authors":"Jean Paul D. Santos, Kamal Bhakta, Foad Fereidoony, Yuanxun Ethan Wang","doi":"10.1049/cds2.12108","DOIUrl":"10.1049/cds2.12108","url":null,"abstract":"Antennas constrained to platforms that require miniaturisation, significantly smaller than the wavelength of the desired frequency, are inefficient radiators and limited to narrowband operations. To overcome these limitations, a technique called direct antenna modulation (DAM), is incorporated with electrically small antennas to enable transmission of high-bandwidth signals through narrowband antennas. DAM utilises switching circuitry to directly modulate the antenna at its corresponding peak energy moments all while being synchronised to the input signal, yet previous iterations were susceptible to low transmit powers due to limitations in the switching network's power handling capability and tremendous coupling between transistor ports that results in an ambiguous switching signal at the gate. A frequency shift keyed (FSK) DAM antenna topology is proposed, which is capable of high-power transmission through a geometrically symmetrical switching circuitry integrating pairs of complementary GaN transistors. The symmetry assists in removing coupling among transistor ports to effectively switch the transistors OFF and ON without regard to the input RF power. The authors’ theoretical analysis agrees with our simulations and far-field measurements which show the FSK DAM antenna topology is capable of transmit powers up to −1 dBm given a 42 dBm of input RF power.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2022-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12108","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124843088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0