Iet Circuits Devices & Systems最新文献_第10页

Improved voltage transfer method for lithium battery string management chip 一种改进的锂电池组管理芯片电压转移方法

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-03-22 DOI: 10.1049/cds2.12060

Kai-Kai Wu, Hong-Yi Wang, Chen Chen, Tao Tao, You-You Fan, Hao Zhang, Yu-Xin Liu

引用次数: 1

Memristor-transistor hybrid ternary content addressable memory using ternary memristive memory cell 使用三元记忆存储器单元的忆阻器-晶体管混合三元内容可寻址存储器

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-03-21 DOI: 10.1049/cds2.12057

Masoodur Rahman Khan, ABM Harun-ur Rashid

{"title":"Memristor-transistor hybrid ternary content addressable memory using ternary memristive memory cell","authors":"Masoodur Rahman Khan, ABM Harun-ur Rashid","doi":"10.1049/cds2.12057","DOIUrl":"10.1049/cds2.12057","url":null,"abstract":"A memristor-transistor hybrid ternary content addressable memory (MTCAM) with a memristor-based ternary memory cell is proposed. New emerging devices like memristors have recently been explored to overcome the limitations of CMOS-based memory circuits. The memristor is used as a binary memory cell in these MTCAM designs to replace a CMOS-based memory cell. This proposed design used a memristor as a ternary memory cell by exploiting its variable resistance characteristics. The associated wiring is reduced almost by a factor of 2 as a ternary cell is used instead of two binary cells. Area efficiency is further enhanced as the MTCAM cell is comprised of two transistors and two memristors (2T2M). A segmentation technique of match line along with a robust write/search operation method is presented to enhance the search speed of the proposed MTCAM. Simulation based on a mathematical model of memristor is presented and analysed using 65 nm TSMC MOS model parameters. Corner simulations and Monte Carlo simulations are carried out to substantiate the robustness of the design against process variation. Simulation results show the worst search delay of 0.75 ns and the energy/bit/search of 0.866 fJ for the 128 × 128 bit MTCAM.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2021-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12057","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115455421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Design and investigation of negative capacitance–based core-shell dopingless nanotube tunnel field-effect transistor 负电容型无掺杂纳米管隧道场效应晶体管的设计与研究

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-03-21 DOI: 10.1049/cds2.12064

Apoorva, Naveen Kumar, S. Intekhab Amin, Sunny Anand

引用次数: 2

A digital phase-based on-fly offset compensation method for decision feedback equalisers 一种基于数字相位的决策反馈均衡器动态补偿方法

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-03-21 DOI: 10.1049/cds2.12027

Andres Amaya, Javier Ardila, Elkim Roa

引用次数: 0

Fault-tolerant quantum implementation of conventional decoder logic with enable input 具有使能输入的传统解码器逻辑的容错量子实现

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-03-18 DOI: 10.1049/cds2.12036

Laxmidhar Biswal, Bappaditya Mondal, Hafizur Rahaman

{"title":"Fault-tolerant quantum implementation of conventional decoder logic with enable input","authors":"Laxmidhar Biswal, Bappaditya Mondal, Hafizur Rahaman","doi":"10.1049/cds2.12036","DOIUrl":"10.1049/cds2.12036","url":null,"abstract":"Decoherence is the greatest obstacle to the physical realization of scalable quantum computer, jeopardises coherent superposition of the qubit, and makes qubit extremely fragile. Quantum Error Correction Code (QECC), and Fault-tolerant quantum computation collectively could protect qubit and improve scalability. On the other hand, the conventional logic circuit is no more useful in quantum computing due to much difference from quantum logic. However, quantum computer has to perform classical tasks which can be addressed by translating to its equivalent quantum algorithm. Herein, zero-garbage-based reversible and fault-tolerant quantum circuit for 1 : 2, and 2 : 4 Decoder with enable signal using Clifford + T-group are proposed. Further, the design approach to implement n : 2n decoder on fault-tolerant quantum logic in linear T − depth is extended. Besides, performance parameters likely T − count, T − depth, and garbage output have been evaluated for n : 2n decoder.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2021-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12036","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134205965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A 0.6 V 2.7 mW 94.3% locking range injection-locked frequency divider using modified varactor-less Colpitts oscillator topology 一种0.6 V 2.7 mW锁定范围94.3%的注入锁定分频器，采用改进的无变元Colpitts振荡器拓扑结构

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-03-17 DOI: 10.1049/cds2.12056

Zhen Li, Zhenrong Li, Xing Quan, Zeyuan Wang, Xinyu Li, Yiqi Zhuang

引用次数: 1

A low power and soft error resilience guard-gated Quartro-based flip-flop in 45 nm CMOS technology 基于45纳米CMOS技术的低功耗软误差弹性保护门控四分频触发器

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-03-17 DOI: 10.1049/cds2.12052

Sabavat Satheesh Kumar, Kumaravel Sundaram, Sanjeevikumar Padmanaban, Jens Bo Holm-Nielsen, Frede Blaabjerg

{"title":"A low power and soft error resilience guard-gated Quartro-based flip-flop in 45 nm CMOS technology","authors":"Sabavat Satheesh Kumar, Kumaravel Sundaram, Sanjeevikumar Padmanaban, Jens Bo Holm-Nielsen, Frede Blaabjerg","doi":"10.1049/cds2.12052","DOIUrl":"https://doi.org/10.1049/cds2.12052","url":null,"abstract":"Conventional flip-flops are more vulnerable to particle strikes in a radiation environment. To overcome this disadvantage, in the literature, many radiation-hardened flip-flops (FFs) based on techniques like triple modular redundancy, dual interlocked cell, Quatro and guard-gated Quatro cell, and so on, are discussed. The flip-flop realized using radiation hardened by design Quatro cell is named as the improved version of Quatro flip-flop (IVQFF). Single event upset (SEU) at inverter stages of master/slave and at output are the two drawbacks of IVQFF. This study proposes a guard-gated Quatro FF (GQFF) using guard-gated Quatro cell and Muller C-element. To overcome the SEU at inverter stages of IVQFF, in GQFF, the inverter stages are realized in a parallel fashion. A dual-input Muller C-element is connected to the GQFF output stage to mask the SEU and thus maintain the correct output. The proposed GQFF tolerates both single node upset (SNU) and double node upset (DNU). It also achieves low power. To prove the efficacy, GQFF and the existing FFs are implemented in 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology. From the simulation results, it may be noted that the GQFF is 100% immune to SNUs and 50% immune to DNUs.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2021-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12052","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"92299664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Dual feedback IRC ring for chaotic waveform generation 用于混沌波形产生的双反馈IRC环

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-03-15 DOI: 10.1049/cds2.12054

Manoj Joshi, Ashish Ranjan

引用次数: 4

Dynamically tuneable pre-modulation filter for an airborne PCM/FM telemetry system 机载PCM/FM遥测系统的动态可调谐预调制滤波器

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-03-12 DOI: 10.1049/cds2.12055

Sudarsana Reddy Karnati, Lakshmi Bopanna, Dhanunjay R Jahagirdar

{"title":"Dynamically tuneable pre-modulation filter for an airborne PCM/FM telemetry system","authors":"Sudarsana Reddy Karnati, Lakshmi Bopanna, Dhanunjay R Jahagirdar","doi":"10.1049/cds2.12055","DOIUrl":"10.1049/cds2.12055","url":null,"abstract":"In the conventional airborne telemetry system, the pre-modulation filter with a multi-pole active Bessel filter is preferred to use in Pulse Code Modulator (PCM)/FM transmission. In the existing system, it is not possible to change the cut-off frequency for different data rates dynamically as required in the launch scenario of a long-range aerospace vehicle. In general, aerospace vehicle has multiple propellant stages to travel a desired trajectory path. Each stage gets separated from the vehicle at different instances. Each stage measurement plan is defined and correspondingly the PCM format is generated with an optimum data rate. Hence, the telemetry system is required to transmit variable data rates at various instances of a long-range aerospace vehicle from launch point to end point of a vehicle. This can be addressed by designing a dynamically tuneable pre-modulation (DTPM) filter. Here, a suitable DTPM filter scheme is proposed to mitigate variable data rate transmission in the telemetry system. The scheme is analysed as per IRIG-106 standard and simulated using MATLAB. The same has been modelled using VHDL and implemented targeting 28 nm technology Xilinx Zynq FPGA device.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2021-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12055","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127819248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fast OMP algorithm and its FPGA implementation for compressed sensing-based sparse signal acquisition systems 基于压缩感知的稀疏信号采集系统的快速OMP算法及其FPGA实现

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-03-12 DOI: 10.1049/cds2.12047

Shirshendu Roy, Debiprasad P. Acharya, Ajit K. Sahoo

{"title":"Fast OMP algorithm and its FPGA implementation for compressed sensing-based sparse signal acquisition systems","authors":"Shirshendu Roy, Debiprasad P. Acharya, Ajit K. Sahoo","doi":"10.1049/cds2.12047","DOIUrl":"https://doi.org/10.1049/cds2.12047","url":null,"abstract":"Compressed sensing-based radio frequency signal acquisition systems call for higher reconstruction speed and low dynamic power. In this study, a novel low power fast orthogonal matching pursuit (LPF-OMP) algorithm is proposed for faster reconstruction of sparse signals from their compressively sensed samples and the reconstruction circuit consumes very low dynamic power. The searching time to find the best column is reduced by reducing the number of columns to be searched in successive iterations. A novel architecture of the proposed LPF-OMP algorithm is also presented here. The proposed architecture is implemented on field programmable gate array for demonstrating the performance enhancement. Computation of pseudoinverse in OMP is avoided to save time and storage requirement to store the pseudoinverse matrix. The proposed design incorporates a novel strategy to stop the algorithm without consuming any extra circuitry. A case study is carried out to reconstruct the RADAR test pulses. The design is implemented for K = 256, N = 1024 using XILINX Virtex6 device and supports maximum of K/4 iterations. The proposed design is faster, hardware efficient and consumes very less dynamic power than the previous implementations of OMP. In addition, the proposed implementation proves to be efficient in reconstructing low sparse signals.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2021-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12047","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"92337063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2