Iet Circuits Devices & Systems最新文献_第10页

Combined feedback–feedforward control of Ćuk CCM converter for achieving fast transient response 为实现快速瞬态响应，Ćuk CCM变换器的联合反馈-前馈控制

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-05-19 DOI: 10.1049/cds2.12085

Byeongcheol Han, Seok-Min Wi, Minsung Kim

{"title":"Combined feedback–feedforward control of Ćuk CCM converter for achieving fast transient response","authors":"Byeongcheol Han, Seok-Min Wi, Minsung Kim","doi":"10.1049/cds2.12085","DOIUrl":"10.1049/cds2.12085","url":null,"abstract":"The Ćuk converters operating in continuous conduction mode (CCM) can be preferred in applications such as microprocessor power delivery and pulsed load because these circuits have advantages of being able to step up/down, a small number of power components, and low input/output current ripples. However, they show poor transient performance due to right-half-plane-zeros (RHPZs) in the closed-loop transfer function of the Ćuk CCM converter. To enhance the transient response, a combined feedback–feedforward control for the Ćuk CCM converter is proposed. The proposed control scheme comprises a feedback control signal based on a Lyapunov function and a duty-ratio feedforward control signal. A Lyapunov-function-based controller (LBC) achieves fast dynamic response even under large-signal variations from the operating point. The duty ratio feedforward controller (DFFC) is developed to predict the effect of the disturbances and compensate it, while alleviating the burden of LBC. The proposed control logic makes the closed-loop system of the Ćuk CCM converter globally exponentially stable and thus provides a fast transient response even under large-signal variations. To construct the proposed controller, the authors make use of the large-signal averaged model of the Ćuk CCM converter, and consider the parasitic elements. To verify the proposed control scheme, numerical simulations and experimental tests are conducted.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 1","pages":"71-80"},"PeriodicalIF":1.3,"publicationDate":"2021-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12085","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117172824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimal sensor placement of bridge structure based on sensitivity-effective independence method 基于灵敏度-有效独立法的桥梁结构传感器优化布置

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-05-11 DOI: 10.1049/cds2.12078

Wenhao Chai, Yaxun Yang, Haibo Yu, Fuli Yang, Zhikui Yang

引用次数: 2

Characterizing a standard cell library for large scale design of memristive based signal processing 描述了一种基于记忆的大规模信号处理设计的标准单元库

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-05-07 DOI: 10.1049/cds2.12076

Abubaker Sasi, Arash Ahmadi, Majid Ahmadi

{"title":"Characterizing a standard cell library for large scale design of memristive based signal processing","authors":"Abubaker Sasi, Arash Ahmadi, Majid Ahmadi","doi":"10.1049/cds2.12076","DOIUrl":"10.1049/cds2.12076","url":null,"abstract":"In recent years, the use of memristors in circuits design has rapidly increased and attracted research interest. Advances have been made to both the size and the complexity of memristor designs. Therefore, computer aided design tools are required to handle memristor-based large-scale designs. A comprehensive automatic framework for the design and synthesis of large-scale memristor-complementary metal-oxide-semiconductor (CMOS) circuits is described herein. This framework provides a synthesis approach that can be applied to all memristor-based digital logic designs. In particular, it is a proposal for a characterization methodology of memristor-based logic cells to generate a standard cell library file for large-scale simulation. The proposed architecture is based on RRAM and ReRAM redox-based devices and the memristor ratioed logic design approach. The proposed framework is implemented in the Cadence Virtuoso schematic-level environment and was verified with Verilog-XL, MATLAB, and the electronic design automation synopses compiler after being translated to the behavioral level. The proposed method can be applied to implement any digital logic design. Nevertheless, it is perfectly suitable for signal processing applications that require MATLAB functions to produce text files with hex values in order to overcome the limitations of the simulation environment. A framework is deployed herein for design of the memristor-based parallel 8-bit adder/subtractor and a 2D memristive-based median filter. Both proposed designs memristor-based adder/subtractor and memristive median filter have significant power reductions of 66% and 16% respectively, when compared to the same designs using CMOS technology.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 1","pages":"13-25"},"PeriodicalIF":1.3,"publicationDate":"2021-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12076","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114048842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FPGACam: A FPGA based efficient camera interfacing architecture for real time video processing FPGACam:一种基于FPGA的高效摄像机接口架构，用于实时视频处理

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-05-07 DOI: 10.1049/cds2.12074

Sayantam Sarkar, Satish S. Bhairannawar, Raja K.B.

{"title":"FPGACam: A FPGA based efficient camera interfacing architecture for real time video processing","authors":"Sayantam Sarkar, Satish S. Bhairannawar, Raja K.B.","doi":"10.1049/cds2.12074","DOIUrl":"10.1049/cds2.12074","url":null,"abstract":"In most of the real time video processing applications, cameras are used to capture live video with embedded systems/Field Programmable Gate Arrays (FPGAs) to process and convert it into the suitable format supported by display devices. In such cases, the interface between the camera and display device plays a vital role with respect to the quality of the captured and displayed video, respectively. In this paper, we propose an efficient FPGA-based low cost Complementary Metal Oxide Semiconductor (CMOS) camera interfacing architecture for live video streaming and processing applications. The novelty of our work is the design of optimised architectures for Controllers, Converters, and several interfacing blocks to extract and process the video frames in real time efficiently. The flexibility of parallelism has been exploited in the design for Image Capture and Video Graphics Array (VGA) Generator blocks. The Display Data Channel Conversion block required for VGA to High Definition Multimedia Interface Conversion has been modified to suit our objective by using optimised Finite State Machine and Transition Minimiszed Differential Signalling Encoder through the use of simple logic architectures, respectively. The hardware utilization of the entire architecture is compared with the existing one which shows that the proposed architecture requires nearly 44% less hardware resources than the existing one.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"15 8","pages":"814-829"},"PeriodicalIF":1.3,"publicationDate":"2021-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12074","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127556203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

CMOS X-band pole-converging triple-cascode LNA with low-noise and wideband performance 具有低噪声和宽带性能的CMOS x波段极点收敛三级联码LNA

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-05-02 DOI: 10.1049/cds2.12081

Cheng Cao, Yubing Li, Zhe Wang, Zemeng Huang, Tao Tan, Deyang Chen, Xiuping Li

引用次数: 6

Constant frequency, non-isolated multichannel LED driver based on variable inductor 基于可变电感的恒频、非隔离多通道LED驱动器

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-04-26 DOI: 10.1049/cds2.12072

Guozhuang Liang, Hanlei Tian, Hetong Wang, Yiwen Xia, Xianyong Xiao

引用次数: 1

Very large scale integration implementation of seizure detection system with on-chip support vector machine classifier 基于片上支持向量机分类器的癫痫检测系统的大规模集成实现

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-04-26 DOI: 10.1049/cds2.12077

Shalini Shanmugam, Selvathi Dharmar

{"title":"Very large scale integration implementation of seizure detection system with on-chip support vector machine classifier","authors":"Shalini Shanmugam, Selvathi Dharmar","doi":"10.1049/cds2.12077","DOIUrl":"10.1049/cds2.12077","url":null,"abstract":"Epilepsy is one of the most common neurological disorders; it affects millions of people globally. Because of the risks to health that it causes, the study and analysis of epilepsy have been given considerable attention in the biomedical field. In a neurological diagnosis, an automated device for detecting seizures or epilepsy from an electroencephalogram (EEG) signal has a significant role. This research work proposes a very large scale integration implementation system for the automatic detection of seizures. Before classification, feature extraction was performed by discrete wavelet transform (DWT) and on-chip classification was performed by a linear support vector machine. The polyphase architecture of Daubechies fourth-order wavelet three-level DWT was used to minimize computational time. The systolic array architecture-based support vector machine classifier using parallel processing helps to minimize the computational complexity of the proposed method. This research work uses an open access EEG dataset. Hardware implementation was done on a field-programmable gate array (FPGA). Efficient results were produced compared with the existing system on chip (SoC) and FPGA seizure detection systems.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 1","pages":"1-12"},"PeriodicalIF":1.3,"publicationDate":"2021-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12077","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"57692022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Regenerative comparator with floating capacitor for energy-harvesting applications 用于能量收集应用的带有浮动电容的再生比较器

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-04-22 DOI: 10.1049/cds2.12073

Hadi Pahlavanzadeh, Mohammad Azim Karami

引用次数: 3

TVD-PB logic circuit based on camouflaging circuit for IoT security 基于伪装电路的物联网安全TVD-PB逻辑电路

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-04-22 DOI: 10.1049/cds2.12080

Yuejun Zhang, Qiufeng Wu, Pengjun Wang, Liang Wen, Zhicun Luan, Chongyan Gu

{"title":"TVD-PB logic circuit based on camouflaging circuit for IoT security","authors":"Yuejun Zhang, Qiufeng Wu, Pengjun Wang, Liang Wen, Zhicun Luan, Chongyan Gu","doi":"10.1049/cds2.12080","DOIUrl":"10.1049/cds2.12080","url":null,"abstract":"Internet of Things (IoT) devices are vulnerable to many physical attacks, including reverse engineering and side-channel analysis because the sensitive information of circuits may be leaked through the physical characteristics of the device. A logic camouflaging circuit is proposed that uses a balanced power consumption and threshold voltage-defined technique to provide an antiphysical attack scheme to protect the hardware security for IoT devices. The proposed circuit uses a symmetric differential pull-down network in implementing the different logic functions through the threshold voltage reconfiguration circuit. As a result, the power consumption of the circuit attains balance and stability between two different logical operations. The proposed threshold voltage-defined power-balance (TVD-PB) design is fabricated using a 65-nm CMOS technology, and the core area occupies approximately 0.0044 mm2, composed of NAND, NOR, XOR, and INV components and multiplier gates of the proposed TVD-PB circuit. The entire chip passed the logic function tests. The measured results show that the average similarity of the TVD-PB universal gate is 99.68%. In addition, the current margin is higher than 55 μA and power consumption of 0.455 mW during each clock cycle at 1.2 V derives 0.1072% of the normalized energy deviation and 0.0453% of the normalized standard deviation. Compared with other state-of-the-art techniques, the power dependency against power attacks is improved effectively.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 1","pages":"40-52"},"PeriodicalIF":1.3,"publicationDate":"2021-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12080","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127372363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Ultrawideband LNA 1960–2019: Review 超宽带LNA 1960-2019:综述

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-04-22 DOI: 10.1049/cds2.12071

Shahab Shahrabadi

{"title":"Ultrawideband LNA 1960–2019: Review","authors":"Shahab Shahrabadi","doi":"10.1049/cds2.12071","DOIUrl":"10.1049/cds2.12071","url":null,"abstract":"To the best of the author's knowledge, several studies during 1960–2019 were carried out on wideband and ultrawideband LNAs just to render optimum LNAs for SAW-less Radio-Frequency Integrated Circuits (RFICs) but none of these works reviewed and taught the proceedings of these six decades, hence the lack of a comprehensive review is quite noticeable. This article specifically studies the challenges and solutions of designing UWB LNA by reviewing topologies and techniques such as inductive peaking, noise and distortion cancellation, gm-boosting, active inductor and notch filter. Its historical aspect illustrates when the idea of wideband LNA was born and how it changed to ultrawideband LNA, and its tutorial aspect discusses circuits and achievements to present optimum LNAs in Complementary MOS (CMOS), BiCMOS and High-Electron-Mobility Transistor (HEMT) technologies. This work describes the endeavours of engineers in reaching UWB LNA from narrowband LNA during six decades that have great importance as a chapter in understanding this topic because it teaches all topologies, techniques, circuits and related events in a historical narrative for trained readers who are not experts on this topic.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"15 8","pages":"697-727"},"PeriodicalIF":1.3,"publicationDate":"2021-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12071","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115483100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6