Characterizing a standard cell library for large scale design of memristive based signal processing

Abstract

In recent years, the use of memristors in circuits design has rapidly increased and attracted research interest. Advances have been made to both the size and the complexity of memristor designs. Therefore, computer aided design tools are required to handle memristor-based large-scale designs. A comprehensive automatic framework for the design and synthesis of large-scale memristor-complementary metal-oxide-semiconductor (CMOS) circuits is described herein. This framework provides a synthesis approach that can be applied to all memristor-based digital logic designs. In particular, it is a proposal for a characterization methodology of memristor-based logic cells to generate a standard cell library file for large-scale simulation. The proposed architecture is based on RRAM and ReRAM redox-based devices and the memristor ratioed logic design approach. The proposed framework is implemented in the Cadence Virtuoso schematic-level environment and was verified with Verilog-XL, MATLAB, and the electronic design automation synopses compiler after being translated to the behavioral level. The proposed method can be applied to implement any digital logic design. Nevertheless, it is perfectly suitable for signal processing applications that require MATLAB functions to produce text files with hex values in order to overcome the limitations of the simulation environment. A framework is deployed herein for design of the memristor-based parallel 8-bit adder/subtractor and a 2D memristive-based median filter. Both proposed designs memristor-based adder/subtractor and memristive median filter have significant power reductions of 66% and 16% respectively, when compared to the same designs using CMOS technology.