Iet Circuits Devices & Systems最新文献

Fast-Locking Frequency-Hopping PLL Using Dual-Edge Low-Duty-Cycle PFD With Cycle Slip Suppression 采用带周跳抑制的双边低占空比PFD的快速锁定跳频锁相环

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-03-30 DOI: 10.1049/cds2/9011136

Afifeh Ghaemnia, Jincheng Yang, Xiaojiong Fei, Guoqiang Zhang

{"title":"Fast-Locking Frequency-Hopping PLL Using Dual-Edge Low-Duty-Cycle PFD With Cycle Slip Suppression","authors":"Afifeh Ghaemnia, Jincheng Yang, Xiaojiong Fei, Guoqiang Zhang","doi":"10.1049/cds2/9011136","DOIUrl":"10.1049/cds2/9011136","url":null,"abstract":"The performance of conventional phase–frequency detectors (PFDs) is critically limited by dead-zone and blind-zone artifacts, which stem from the timing constraints of D flip-flop (DFF) based architectures. These non-idealities degrade phase-detection resolution, induce cycle slip, and prolong the lock time of phase-locked loops (PLLs). This paper introduces a dual-edge low-duty-cycle PFD (DELD–PFD) that utilizes high-speed feed-through and output-prediction logic flip-flops to detect both rising and falling edges of the input clocks, thereby eliminating the dead and blind zones and enhancing phase resolution. The proposed architecture inherently generates low-duty-cycle output pulses, which reduces charge-pump current mismatch and improves loop dynamics. Fabricated in a standard 55 nm CMOS technology, the post-layout simulation results validate operation across 1 MHz–5.5 GHz. The DELD–PFD achieves a lock-time reduction of 63% relative to a conventional PLL, consumes 74 µW at 5 GHz from a 1.2 V supply, and delivers a phase noise of –147 dBc/Hz at a 1 MHz offset. Comprehensive Monte Carlo and PVT (process, voltage, and temperature) simulations confirm robustness across variations, demonstrating the design’s suitability for high-speed, low-noise, frequency-hopping PLL applications.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2026-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/9011136","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147668937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fast Efficient Solar Cell Simulator 快速高效太阳能电池模拟器

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-03-02 DOI: 10.1049/cds2/7856894

Supriyo Karmakar

引用次数: 0

Fast Efficient Solar Cell Simulator 快速高效太阳能电池模拟器

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-03-02 DOI: 10.1049/cds2/7856894

Supriyo Karmakar

引用次数: 0

Analysis and Evaluation of Approximate Ripple-Carry Adders in the Presence of a Single Functional Error (SFE) 存在单函数误差（SFE）的近似纹波进位加法器分析与评价

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-02-27 DOI: 10.1049/cds2/9917935

Junqi Huang, T. Nandha Kumar, Haider A. F. Almurib, Fabrizio Lombardi

{"title":"Analysis and Evaluation of Approximate Ripple-Carry Adders in the Presence of a Single Functional Error (SFE)","authors":"Junqi Huang, T. Nandha Kumar, Haider A. F. Almurib, Fabrizio Lombardi","doi":"10.1049/cds2/9917935","DOIUrl":"https://doi.org/10.1049/cds2/9917935","url":null,"abstract":"As widely used in arithmetic circuits (such as a ripple carry adder [RCA]), approximate computing intentionally introduces errors in the design; however, approximate circuits can also experience errors due to external and physical phenomena (such as cosmic rays or a stuck-at). These errors can be analyzed by their functional nature. This article examines the impact of a single functional error (SFE) in both an approximate cell as well as the entire RCA. The study analyzes exact and approximate cell designs using a state transition diagram-based approach to understand the relationships between different types of functional error and the expected behavior in all possible scenarios. The article also proposes a probabilistic analysis for an exact RCA, which aligns well with simulation results for several metrics, such as the error rate (ER). Additionally, an error analysis is conducted on the RCA by considering the number of approximate cells and the location of the single erroneous cell. The results and modeling analysis of the exact RCA show that the ER and the mean error distance (MED) for Carry in (Cin) = 0 are higher than for Cin = 1; furthermore, the MED for an approximate RCA in the presence of an SFE is higher than for the exact RCA. These findings indicate that an approximate RCA affected by an SFE incurs a significantly degraded accuracy as related to the approximate cell type. Finally, the article provides a binary tree-based analysis to support the comprehensive simulation results for the RCA’s ER using different approximate cells.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2026-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/9917935","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147569591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis and Evaluation of Approximate Ripple-Carry Adders in the Presence of a Single Functional Error (SFE) 存在单函数误差（SFE）的近似纹波进位加法器分析与评价

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-02-27 DOI: 10.1049/cds2/9917935

Junqi Huang, T. Nandha Kumar, Haider A. F. Almurib, Fabrizio Lombardi

{"title":"Analysis and Evaluation of Approximate Ripple-Carry Adders in the Presence of a Single Functional Error (SFE)","authors":"Junqi Huang, T. Nandha Kumar, Haider A. F. Almurib, Fabrizio Lombardi","doi":"10.1049/cds2/9917935","DOIUrl":"10.1049/cds2/9917935","url":null,"abstract":"As widely used in arithmetic circuits (such as a ripple carry adder [RCA]), approximate computing intentionally introduces errors in the design; however, approximate circuits can also experience errors due to external and physical phenomena (such as cosmic rays or a stuck-at). These errors can be analyzed by their functional nature. This article examines the impact of a single functional error (SFE) in both an approximate cell as well as the entire RCA. The study analyzes exact and approximate cell designs using a state transition diagram-based approach to understand the relationships between different types of functional error and the expected behavior in all possible scenarios. The article also proposes a probabilistic analysis for an exact RCA, which aligns well with simulation results for several metrics, such as the error rate (ER). Additionally, an error analysis is conducted on the RCA by considering the number of approximate cells and the location of the single erroneous cell. The results and modeling analysis of the exact RCA show that the ER and the mean error distance (MED) for Carry in (Cin) = 0 are higher than for Cin = 1; furthermore, the MED for an approximate RCA in the presence of an SFE is higher than for the exact RCA. These findings indicate that an approximate RCA affected by an SFE incurs a significantly degraded accuracy as related to the approximate cell type. Finally, the article provides a binary tree-based analysis to support the comprehensive simulation results for the RCA’s ER using different approximate cells.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2026-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/9917935","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147569590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An FSM-Enabled Reconfigurable Debugging Approach for Area-Optimized FIR Filters on FPGA Platforms FPGA平台上区域优化FIR滤波器的fsm可重构调试方法

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-02-17 DOI: 10.1049/cds2/5545245

Murali Anumothu, G. M. Anitha Priyadarshini, Ch. Hima Bindu, Rajanikanth Aluvalu, Sai Prashanth Mallellu, Pankaj Kumar, Ghanshyam G. Tejani, Seyed Jalaleddin Mousavirad

{"title":"An FSM-Enabled Reconfigurable Debugging Approach for Area-Optimized FIR Filters on FPGA Platforms","authors":"Murali Anumothu, G. M. Anitha Priyadarshini, Ch. Hima Bindu, Rajanikanth Aluvalu, Sai Prashanth Mallellu, Pankaj Kumar, Ghanshyam G. Tejani, Seyed Jalaleddin Mousavirad","doi":"10.1049/cds2/5545245","DOIUrl":"https://doi.org/10.1049/cds2/5545245","url":null,"abstract":"This work introduces a novel method to improve hardware debugging efficiency and decrease computing time by employing a finite state machine (FSM)-based reconfigurable buffer insertion strategy for optimizing field-programmable gate array (FPGA) performance. The proposed strategy greatly enhances the debugging process by offering a systematic approach for error discovery, so ensuring that the FPGA functions with diminished complexity and increased dependability. Additionally, a reconfigurable decision tree generation (DTG)-finite impulse response (FIR) filter design is shown to optimize circuit area, resulting in a decrease in the quantity of stored memory look-up tables (LUTs). The substantial enhancement in power efficiency and area attained by using 4 LUTs in place of 6 LUTs. This work executes and verifies the register-transfer level (RTL) functionality by operating with 16 taps. This idea depends on the usage of an FSM controller for the utilization of a common buffer. This buffer eliminates the usage of 16 distinct buffers by sharing all 16 taps in order to identify errors. With this approach, the simplified design and overall efficiency are improved. This approach achieves improved debug capabilities with a single common buffer by eliminating usage of multiple buffers. The hardware complexity of the circuit is decreased substantially by using this proposed model. This model proves that the suggested FSM-based buffer insertion and reconfigurable FIR filter design improve computational efficiency and FPGA area optimization, positioning it as a viable alternative for forthcoming FPGA-based designs.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2026-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/5545245","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147315457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An FSM-Enabled Reconfigurable Debugging Approach for Area-Optimized FIR Filters on FPGA Platforms FPGA平台上区域优化FIR滤波器的fsm可重构调试方法

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-02-17 DOI: 10.1049/cds2/5545245

Murali Anumothu, G. M. Anitha Priyadarshini, Ch. Hima Bindu, Rajanikanth Aluvalu, Sai Prashanth Mallellu, Pankaj Kumar, Ghanshyam G. Tejani, Seyed Jalaleddin Mousavirad

{"title":"An FSM-Enabled Reconfigurable Debugging Approach for Area-Optimized FIR Filters on FPGA Platforms","authors":"Murali Anumothu, G. M. Anitha Priyadarshini, Ch. Hima Bindu, Rajanikanth Aluvalu, Sai Prashanth Mallellu, Pankaj Kumar, Ghanshyam G. Tejani, Seyed Jalaleddin Mousavirad","doi":"10.1049/cds2/5545245","DOIUrl":"10.1049/cds2/5545245","url":null,"abstract":"This work introduces a novel method to improve hardware debugging efficiency and decrease computing time by employing a finite state machine (FSM)-based reconfigurable buffer insertion strategy for optimizing field-programmable gate array (FPGA) performance. The proposed strategy greatly enhances the debugging process by offering a systematic approach for error discovery, so ensuring that the FPGA functions with diminished complexity and increased dependability. Additionally, a reconfigurable decision tree generation (DTG)-finite impulse response (FIR) filter design is shown to optimize circuit area, resulting in a decrease in the quantity of stored memory look-up tables (LUTs). The substantial enhancement in power efficiency and area attained by using 4 LUTs in place of 6 LUTs. This work executes and verifies the register-transfer level (RTL) functionality by operating with 16 taps. This idea depends on the usage of an FSM controller for the utilization of a common buffer. This buffer eliminates the usage of 16 distinct buffers by sharing all 16 taps in order to identify errors. With this approach, the simplified design and overall efficiency are improved. This approach achieves improved debug capabilities with a single common buffer by eliminating usage of multiple buffers. The hardware complexity of the circuit is decreased substantially by using this proposed model. This model proves that the suggested FSM-based buffer insertion and reconfigurable FIR filter design improve computational efficiency and FPGA area optimization, positioning it as a viable alternative for forthcoming FPGA-based designs.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2026-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/5545245","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147315456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Smart City Lighting for All Ages: Age-Adaptive Fuzzy Systems for Real-Time Energy Management 适合所有年龄的智慧城市照明：用于实时能源管理的年龄自适应模糊系统

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-02-07 DOI: 10.1049/cds2/9991771

Mohammad Javad Kalani, Mahdi Kalani

{"title":"Smart City Lighting for All Ages: Age-Adaptive Fuzzy Systems for Real-Time Energy Management","authors":"Mohammad Javad Kalani, Mahdi Kalani","doi":"10.1049/cds2/9991771","DOIUrl":"https://doi.org/10.1049/cds2/9991771","url":null,"abstract":"Taking advantage of cutting-edge technologies to efficiently control energy consumption while prioritizing public well-being is a wise choice for the sustainable development of cities and societies. From this perspective, the proposed approach in this study, which employs real-time electricity pricing, user age, and user preferences as input parameters for a fuzzy inference system (FIS), aims to balance energy consumption along with people’s lighting requirements. FISs based on linguistic patterns are ideal for establishing communication between individuals and artificial intelligence, especially in smart cities. FIS allows complicated parameters to be defined in a flexible framework that is easily understandable to humans. While this study specifically evaluated the performance of the proposed system for lighting demands, it may also be applied to other purposes and requirements. Results from the system simulations for a commercial setting validate the suggested system’s accuracy. According to the findings, developing appropriate control strategies derived from the established method enables meeting users’ lighting requirements for individuals of different ages. At the same time, this method regulates energy consumption and associated costs. The introduced method is advocated as an innovative solution for developing smarter and more sustainable cities and societies.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2026-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/9991771","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146256310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Smart City Lighting for All Ages: Age-Adaptive Fuzzy Systems for Real-Time Energy Management 适合所有年龄的智慧城市照明：用于实时能源管理的年龄自适应模糊系统

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-02-07 DOI: 10.1049/cds2/9991771

Mohammad Javad Kalani, Mahdi Kalani

{"title":"Smart City Lighting for All Ages: Age-Adaptive Fuzzy Systems for Real-Time Energy Management","authors":"Mohammad Javad Kalani, Mahdi Kalani","doi":"10.1049/cds2/9991771","DOIUrl":"10.1049/cds2/9991771","url":null,"abstract":"Taking advantage of cutting-edge technologies to efficiently control energy consumption while prioritizing public well-being is a wise choice for the sustainable development of cities and societies. From this perspective, the proposed approach in this study, which employs real-time electricity pricing, user age, and user preferences as input parameters for a fuzzy inference system (FIS), aims to balance energy consumption along with people’s lighting requirements. FISs based on linguistic patterns are ideal for establishing communication between individuals and artificial intelligence, especially in smart cities. FIS allows complicated parameters to be defined in a flexible framework that is easily understandable to humans. While this study specifically evaluated the performance of the proposed system for lighting demands, it may also be applied to other purposes and requirements. Results from the system simulations for a commercial setting validate the suggested system’s accuracy. According to the findings, developing appropriate control strategies derived from the established method enables meeting users’ lighting requirements for individuals of different ages. At the same time, this method regulates energy consumption and associated costs. The introduced method is advocated as an innovative solution for developing smarter and more sustainable cities and societies.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2026-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/9991771","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146256309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Partition Border Tuning and Chattering Mitigation for DC–DC Series Resonant Converters: A Stability-Oriented Approach DC-DC串联谐振变换器的分割边界调谐和颤振抑制：一种面向稳定性的方法

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-01-31 DOI: 10.1049/cds2/9961947

Mahdi Vakilfard, Asghar Taheri, Amir Ghasemian

引用次数: 0