Iet Circuits Devices & Systems最新文献

Design and Simulation of a Wideband 3-Bit Phase Shifter for 4.5–5.5 GHz Applications 4.5-5.5 GHz宽带3位移相器的设计与仿真

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-09-29 DOI: 10.1049/cds2/5377138

Sena Taş, Fırat Kaçar

引用次数: 0

A Review of Performance and Reliability Issues in D Flip-Flops for Future Artificial Intelligence and Internet of Things Applications 面向未来人工智能和物联网应用的D触发器性能和可靠性问题综述

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-09-26 DOI: 10.1049/cds2/7132642

Syeda Hurmath Juveria, R. Shashank, J. Ajayan, Amit Krishna Dwivedi, D. Nirmal

{"title":"A Review of Performance and Reliability Issues in D Flip-Flops for Future Artificial Intelligence and Internet of Things Applications","authors":"Syeda Hurmath Juveria, R. Shashank, J. Ajayan, Amit Krishna Dwivedi, D. Nirmal","doi":"10.1049/cds2/7132642","DOIUrl":"https://doi.org/10.1049/cds2/7132642","url":null,"abstract":"In this paper, various D flip-flops (FFs) (DFFs) are studied and analyzed based on the performance and reliability effects of different architectures, technology, area, power, delay, and several other key performance parameters of DFFs. Based on these parameters, a few selected DFFs such as C2SFF, conditional-bridging FF (CBFF)-S, self-shut-off pulsed latch (SSPL), retentive true signal phased clock (R-TSPC), mTGFF, mC2MOS, FS-TSPC-DET-FF, and P-FF, are briefly reviewed for different architectures and technologies, with the trade-off between the various performance parameters discussed in this paper. Comparative analysis is done for the selected DFFs on technology, supply voltage, set-up time, delay, power consumption, and area. Reliability effects on DFFs and aging effect on FFs are reviewed for timing yield-aware lifetime reliability (TYR) based on the process variations (PVs) and bias temperature instability (BTI). A brief review on applications of DFFs in internet of thing (IoT) devices and artificial intelligence (AI), such as frequency divider, dual-modulus prescaler, time-to-digital converter (TDC), shifter, and synchronizer, is also presented.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/7132642","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145146600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Generic PEH Interface Circuit With an Improved Environmental Adaptivity Using a Post Implementation Calibration Technique 采用后校正技术改进环境适应性的通用PEH接口电路

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-09-26 DOI: 10.1049/cds2/9226422

Saman Shoorabi Sani

{"title":"Generic PEH Interface Circuit With an Improved Environmental Adaptivity Using a Post Implementation Calibration Technique","authors":"Saman Shoorabi Sani","doi":"10.1049/cds2/9226422","DOIUrl":"https://doi.org/10.1049/cds2/9226422","url":null,"abstract":"This study presents a novel triple-step bias-flip rectifier with a post implementation calibration (PIC) scheme to address both the need for a general-purpose adaptable piezoelectric energy harvester (PEH) interface circuit (PEHIC) and the PVT-related issues while maintaining acceptable efficiency and a smaller inductor. Due to the PIC, the proposed circuit is adaptable to various piezoelectric materials and inductors. Using a 100-µH inductor, a 180 nm standard design kit, and an energy investing (EI) scheme, the proposed rectifier achieves a bias flip efficiency of 100%. Without EI, the proposed circuit achieves the recently reported high bias flip efficiency, that is, ɳflip, in the literature with a considerably smaller inductor. According to simulation results, the improvement of the designed circuit relative to the full bridge rectifier (FBR) falls within the scope of 2–3.8. Postsimulation calculations revealed that the figure of merit of adaptivity, that is, FoMadaptivity, of the proposed circuit is approximately 83.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/9226422","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145146601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Network Reconfiguration Approach for Service Restoration Based on a Novel and Multiobjective Optimization Method 基于新型多目标优化方法的服务恢复网络重构方法

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-09-16 DOI: 10.1049/cds2/1992253

Iman Nik, Majid Halaji, Mohammad Hossein Yazdi, Javad Safehian, Ali Asghar Shojaei

{"title":"A Network Reconfiguration Approach for Service Restoration Based on a Novel and Multiobjective Optimization Method","authors":"Iman Nik, Majid Halaji, Mohammad Hossein Yazdi, Javad Safehian, Ali Asghar Shojaei","doi":"10.1049/cds2/1992253","DOIUrl":"10.1049/cds2/1992253","url":null,"abstract":"Restoring load following partial outages or local faults in a section of the distribution system, as addressed in this study, is crucial to minimizing service interruptions and financial damages. Reconfiguring the network is a crucial first step in load restoration. The presence of distributed generation (DG) units, in addition to the reconfiguration of the distribution network, can be very effective in the load recovery process. Therefore, in this study, the problem of reconfiguring the distribution network in the presence of DG units and charging stations of electric vehicles with the goals of reducing energy not supplied (ENS) and losses has been solved. The suggested problem is resolved by introducing and putting into practice the hybrid particle swarm optimization and shuffled frog leaping (HPSO-SFL) algorithm, which is based on hybrid swarm intelligence. The effectiveness and accuracy of the proposed method are validated using a 33-bus test system under multiple scenarios. To assess its performance, the results are compared against those reported in previous studies. Following network reconfiguration, the power losses were reduced by 45% without DG and by 77% with DG, relative to the initial system state. Furthermore, when electric vehicle charging stations (EVCSs), modeled as active loads, were included in the optimization process, power losses decreased by approximately 23% compared to the pre-reconfiguration condition.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/1992253","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145101633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Improving FinFET Device Parameters Through an Integrated Method of Particle Swarm and Whale Optimization Techniques 基于粒子群和鲸鱼优化技术的改进FinFET器件参数

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-08-28 DOI: 10.1049/cds2/7035085

Vijayalaxmi Kumbar, Manisha Waje

{"title":"Improving FinFET Device Parameters Through an Integrated Method of Particle Swarm and Whale Optimization Techniques","authors":"Vijayalaxmi Kumbar, Manisha Waje","doi":"10.1049/cds2/7035085","DOIUrl":"10.1049/cds2/7035085","url":null,"abstract":"The geometrical parameters of the fin-shaped field-effect transistor (FinFET) significantly affect the outcomes of the FinFET-based designs. Various machine learning (ML) schemes have been presented to optimize the geometrical parameters of the FinFET devices to limit the adverse effect of scaling. This paper presents the FinFET width and height optimization using the proposed hybrid particle swarm optimization algorithm-based whale optimization algorithm (HPSO-WOA). To improve device performance, the whale optimization algorithm (WOA) is utilized to find optimal geometric parameters of FinFET, such as width and height. Meanwhile, the PSO is used to optimize WOA hyperparameters. It uses various parameters such as on-state current, transconductance, subthreshold swing (SS), early voltage (VEA), and transconductance generation factor (TGF) for analyzing the impact of fin width and height on the FinFET device. Additionally, we have analyzed the impact of the proposed parameters on the design of 6-T static random access memory (SRAM). Microwind 3.9 EDA is used to design, simulate, and improve the physical layout utilizing the FinFET 14 nm and BSIM 4 MOS modeling technique. The proposed HPSO-WOA improves 0.17% in SS, 0.62% in gm, 0.05% in TGF, and 70.86% in optimization time over the quasi-random sequence (QRS)-WOA. However, it resulted in overall improvement of 0.90% in SS, 0.74% in gm, 1.05% in TGF, and 173% in optimization time over traditional WOA.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/7035085","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144910197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Adaptive Temperature-Compensation of Charge-Pump PLL–Based MTJ/CMOS for Frequency Stability 基于锁相环的电荷泵MTJ/CMOS频率稳定自适应温度补偿

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-08-27 DOI: 10.1049/cds2/1773323

Chunyu Peng, Jingxue Zhong, Yingxue Sun, Weizhe Tan, Chengxing Dai, Xin Li, Xiulong Wu, Yongliang Zhou

{"title":"Adaptive Temperature-Compensation of Charge-Pump PLL–Based MTJ/CMOS for Frequency Stability","authors":"Chunyu Peng, Jingxue Zhong, Yingxue Sun, Weizhe Tan, Chengxing Dai, Xin Li, Xiulong Wu, Yongliang Zhou","doi":"10.1049/cds2/1773323","DOIUrl":"10.1049/cds2/1773323","url":null,"abstract":"The charge pump phase-locked loop (CP-PLL) is a critical component in modern mixed-signal electronics, widely used for clock generation, synchronization, and frequency synthesis in digital and wireless applications. However, its performance is significantly impacted by nonideal effects, particularly the current mismatch of the charge pump (CP) and the frequency variation of oscillator, both of which are highly sensitive to temperature fluctuations. To address these challenges, this work leverages the positive temperature coefficient (PTC) of the drain-source on-state resistance in CMOS and the negative temperature coefficient (NTC) of the magnetic tunnel junction (MTJ). Using 28 nm CMOS technology, we analyze and simulate the current mismatch of the CP across a wide temperature range, achieving a current mismatch of less than 0.3%. Furthermore, the proposed approach significantly improves the frequency stability of the ring oscillator. Simulation results validate the effectiveness of our design, demonstrating that the MTJ compensates for 90% of the output frequency drift over a temperature range from −80 to 125°C.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/1773323","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144905509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Gate Dielectric Engineering Using Stacked Gate Dielectric in U-Shaped Gate Tunnel FET u型栅隧道场效应管中堆叠栅介电的栅介电工程

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-08-14 DOI: 10.1049/cds2/5014133

Sina Mehrad, Hamid Reza Yaghobi, Kaveh Eyvazi, Mohammad Azim Karami

{"title":"Gate Dielectric Engineering Using Stacked Gate Dielectric in U-Shaped Gate Tunnel FET","authors":"Sina Mehrad, Hamid Reza Yaghobi, Kaveh Eyvazi, Mohammad Azim Karami","doi":"10.1049/cds2/5014133","DOIUrl":"10.1049/cds2/5014133","url":null,"abstract":"In this paper, an innovative approach for the performance enhancement of tunnel field-effect transistors (TFETs) is presented with the introduction of the stacked gate oxide U-shaped tunnel FET (SUTFET). This novel design incorporates a unique combination of titanium dioxide (TiO2) and silicon dioxide (SiO2) layers as stacked gate dielectrics, significantly enhancing device performance. The stacked SUTFET achieves a notable reduction in the OFF-current while delivering a substantial improvement in the ON-current and better subthreshold swing (SS). Our research explores varying the thickness of TiO2 and SiO2 layers effect on critical electrical parameters, including threshold voltage, ON-current, and leakage current. This study reveals that the use of TiO2, with its superior dielectric constant compared to the conventional HfO2, leads to exceptional current capabilities and superior control over the off current. Through detailed simulations, we demonstrate that the adjustment of dielectric thickness can further optimize SS and minimize the leakage. The findings highlight the potential of the stacked gate oxide SUTFET as a major breakthrough in the field of tunnel FETs, paving the way for advancements in high-performance and low-power electronic devices. This novel approach not only addresses key performance limitations of conventional TFET structures but also sets a new benchmark for future research and development in the semiconductor technology.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/5014133","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144832985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A New Zero Current Switching Ultra Step-Up Converter With Low Input Current Ripple 一种新型低输入纹波零电流开关超升压变换器

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-08-06 DOI: 10.1049/cds2/4463224

Eiraj Rezai, Majid Delshad, Bahador Fani

{"title":"A New Zero Current Switching Ultra Step-Up Converter With Low Input Current Ripple","authors":"Eiraj Rezai, Majid Delshad, Bahador Fani","doi":"10.1049/cds2/4463224","DOIUrl":"10.1049/cds2/4463224","url":null,"abstract":"This paper proposes a high step-up converter featuring zero current (ZC) switching (ZCS) and continuous input current to enhance efficiency. The converter integrates switched capacitor and coupled inductor techniques to improve voltage gain while significantly reducing the voltage stress across the switch. Furthermore, the maximum voltage stress on the diodes remains unaffected by the increase in turn ratio, allowing for unrestricted turn ratio adjustment to boost the gain. ZCS is achieved without requiring auxiliary circuitry or extra switches. The use of pulse width modulation (PWM) for the switch simplifies the control circuit implementation. Additionally, the leakage inductance energy is efficiently absorbed by the clamping capacitor, preventing voltage spikes on the switch. Moreover, the switch source is grounded, enabling the drive circuit to be powered directly from the input. The converter is comprehensively analyzed, and both simulation results from PSPICE and experimental implementation results are presented to validate its performance. The results demonstrate a full-load efficiency of 96.2%.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/4463224","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145128860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Multiobjective Strategy for Optimized Load Breaker Switch Placement to Improve Distribution Network Performance and Reliability 配电网性能与可靠性优化的负荷断路器多目标策略

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-07-19 DOI: 10.1049/cds2/8337521

Mohammad Ebrahim Hajiabadi, Hossein Parsadust, Hossein Lotfi, Sajjad Borhani Yazdi, Hossein Ramezani

{"title":"Multiobjective Strategy for Optimized Load Breaker Switch Placement to Improve Distribution Network Performance and Reliability","authors":"Mohammad Ebrahim Hajiabadi, Hossein Parsadust, Hossein Lotfi, Sajjad Borhani Yazdi, Hossein Ramezani","doi":"10.1049/cds2/8337521","DOIUrl":"10.1049/cds2/8337521","url":null,"abstract":"This paper examines the issue of load management in electrical distribution networks, with a focus on the optimal placement of telecommunication load breaker switches (TCLBSs). The main innovation of this study lies in the introduction of a dual-objective optimization framework that simultaneously aims to minimize energy not supplied (ENS) and preserve critical loads. This approach enables network operators to prioritize switch placement based on the importance of each objective, offering a level of flexibility, and comprehensiveness not thoroughly addressed in previous studies. To solve this problem, an iterative graph-based search algorithm is employed, which dynamically identifies the optimal locations for switch installation. By leveraging graph theory, the proposed method significantly reduces computational complexity and enhances responsiveness to changing network conditions. According to simulation results on the IEEE 33-bus network, switch locations change as the priority of critical loads increases, and the proposed strategy greatly improves the reliability and performance of the power distribution network during peak demand periods. This dual-objective approach, with adjustable settings, enhances the efficiency of load management, and strengthens network dependability.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/8337521","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144662903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Research on Real-Time Detail Enhancement Algorithm for Endoscopic Video Images and Hardware Implementation 内窥镜视频图像实时细节增强算法研究及硬件实现

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-07-14 DOI: 10.1049/cds2/4098208

Tianci Wu, Yu Pang, Yuanfa Wang, Wenpeng Su

{"title":"Research on Real-Time Detail Enhancement Algorithm for Endoscopic Video Images and Hardware Implementation","authors":"Tianci Wu, Yu Pang, Yuanfa Wang, Wenpeng Su","doi":"10.1049/cds2/4098208","DOIUrl":"10.1049/cds2/4098208","url":null,"abstract":"In order to solve the problems of low contrast and weak detail information of endoscope images, the image adaptive histogram detail enhancement algorithm is presented. Although the adaptive histogram equalization (AHE) algorithm has been studied in some depth, the detail enhancement algorithm is relatively complicated and difficult to implement in endoscope hardware. In order to realize the real-time and adaptive enhancement of endoscope image details on the hardware system, the AHE algorithm is improved to reduce the hardware resource consumption and time complexity. The improved algorithm selects the segmentation condition suitable for real-time image, the threshold interception, and the pipeline structure to process the low contrast endoscopic image. Xilinx’s Artix-7 chip is used to implement the hardware circuit and process images with a resolution of 640 x 480 in real time at a rate of up to 160 frames per second. The design utilizes 25K look-up tables (LUTs), 6K flip–flops, and 33 block RAMS. The experimental results show that the improved algorithm has the characteristics of fast processing speed, good detail enhancement effect, and strong portability, which can meet the requirements of real-time video processing in endoscopy.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/4098208","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144615367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0