Iet Circuits Devices & Systems最新文献

Analog/RF and Distortion Characteristics of Recessed Superjunction AlGaN/GaN HEMTs 嵌入式超结AlGaN/GaN hemt的模拟/射频和畸变特性

IF 1.8 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-07-28 DOI: 10.1049/cds2/7803942

Nahida Banu, Chandrima Mondal, Abhijit Biswas

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引用次数: 0

Analog/RF and Distortion Characteristics of Recessed Superjunction AlGaN/GaN HEMTs 嵌入式超结AlGaN/GaN hemt的模拟/射频和畸变特性

IF 1.8 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-07-28 DOI: 10.1049/cds2/7803942

Nahida Banu, Chandrima Mondal, Abhijit Biswas

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引用次数: 0

Design and Performance Analysis of Dielectrically Modulated Diagonal Tunneling TFET for Label Free Sensing 无标签传感介质调制对角隧穿TFET的设计与性能分析

IF 1.8 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-07-10 DOI: 10.1049/cds2/3745152

I. Rama Satya Nageswara Rao, Srinivasa Rao Karumuri

{"title":"Design and Performance Analysis of Dielectrically Modulated Diagonal Tunneling TFET for Label Free Sensing","authors":"I. Rama Satya Nageswara Rao, Srinivasa Rao Karumuri","doi":"10.1049/cds2/3745152","DOIUrl":"10.1049/cds2/3745152","url":null,"abstract":"This paper presents a novel architecture the diagonal tunneling dielectrically modulated tunnel field effect transistor (DT-DMTFET) for label-free biosensing applications. The study employs TCAD (Silvaco TCAD) simulations to comprehensively analyze the behavior of the DT-DMTFET biosensor focusing on key parameters such as drain current, sub-threshold slope, surface potential, and the Ion/Ioff ratio. The paper extensively examines the physics of transduction mechanisms for lateral tunneling (LT), vertical tunneling (VT), and diagonal tunneling (DT)–based DMTFETs, considering device electrostatics and transport mechanisms. Simulations include variations in dielectric constants, cavity length and cavity thickness, while incorporating gate and cavity engineering techniques to enhance biosensor performance. The paper quantitatively assesses the transduction efficiency of sensor devices particularly focusing on current sensitivity. The DT-DMTFET exhibits a sensitivity of 4.6 × 103 Ω/volt and observed the sensitivities of 1.7 × 102 Ω/volt and 3.1 × 103 Ω/volt in LT-DMTFET and VT-DMTFET, respectively. Optimal sensitivity for DT-DMTFET is observed at gate voltages of 3–4 V, contrasting with 2 V and 4 V for VT-DMTFET and LT-DMTFET, respectively. Detailed studies on device design aspects identify relevant structural parameters, optimizing the sensing performance of DT-DMTFET. A comprehensive performance comparison establishes that DT-DMTFETs offer over 45% and 100% improvements in current sensitivity compared to their vertical and LT-based counterparts, respectively, across a range of biomolecule sample specifications.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/3745152","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148466792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and Performance Analysis of Dielectrically Modulated Diagonal Tunneling TFET for Label Free Sensing 无标签传感介质调制对角隧穿TFET的设计与性能分析

IF 1.8 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-07-10 DOI: 10.1049/cds2/3745152

I. Rama Satya Nageswara Rao, Srinivasa Rao Karumuri

{"title":"Design and Performance Analysis of Dielectrically Modulated Diagonal Tunneling TFET for Label Free Sensing","authors":"I. Rama Satya Nageswara Rao, Srinivasa Rao Karumuri","doi":"10.1049/cds2/3745152","DOIUrl":"https://doi.org/10.1049/cds2/3745152","url":null,"abstract":"This paper presents a novel architecture the diagonal tunneling dielectrically modulated tunnel field effect transistor (DT-DMTFET) for label-free biosensing applications. The study employs TCAD (Silvaco TCAD) simulations to comprehensively analyze the behavior of the DT-DMTFET biosensor focusing on key parameters such as drain current, sub-threshold slope, surface potential, and the Ion/Ioff ratio. The paper extensively examines the physics of transduction mechanisms for lateral tunneling (LT), vertical tunneling (VT), and diagonal tunneling (DT)–based DMTFETs, considering device electrostatics and transport mechanisms. Simulations include variations in dielectric constants, cavity length and cavity thickness, while incorporating gate and cavity engineering techniques to enhance biosensor performance. The paper quantitatively assesses the transduction efficiency of sensor devices particularly focusing on current sensitivity. The DT-DMTFET exhibits a sensitivity of 4.6 × 103 Ω/volt and observed the sensitivities of 1.7 × 102 Ω/volt and 3.1 × 103 Ω/volt in LT-DMTFET and VT-DMTFET, respectively. Optimal sensitivity for DT-DMTFET is observed at gate voltages of 3–4 V, contrasting with 2 V and 4 V for VT-DMTFET and LT-DMTFET, respectively. Detailed studies on device design aspects identify relevant structural parameters, optimizing the sensing performance of DT-DMTFET. A comprehensive performance comparison establishes that DT-DMTFETs offer over 45% and 100% improvements in current sensitivity compared to their vertical and LT-based counterparts, respectively, across a range of biomolecule sample specifications.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/3745152","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148466793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of Ternary Analog-to-Digital Converter Based on Graphene-MoS2 Heterostructure 基于石墨烯- mos2异质结构的三元模数转换器设计

IF 1.8 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-07-01 DOI: 10.1049/cds2/7817923

Pedram Beyranvand, Behrouz Heidari, Ashkan Horri, Mohammad Bagher Tavakoli

{"title":"Design of Ternary Analog-to-Digital Converter Based on Graphene-MoS2 Heterostructure","authors":"Pedram Beyranvand, Behrouz Heidari, Ashkan Horri, Mohammad Bagher Tavakoli","doi":"10.1049/cds2/7817923","DOIUrl":"https://doi.org/10.1049/cds2/7817923","url":null,"abstract":"This paper presents a 2-bit ternary pipelined analog-to-digital converter (ADC) featuring nine quantization levels, implemented using a Dirac source field-effect transistor (DS-FET). The proposed DS-FET is based on graphene-MoS2 heterostructure, that utilizes modulation of the graphene source’s density of states (DOSs) to generate intermediate electronic states. These states enable the realization of three discrete logic levels, which form the foundation of ternary logic operations. By precisely tuning the doping concentration within the graphene source region, the ternary quantizer can be achieved. By using a two-stage pipelined ADC and employing the quantizer in each stage, ternary ADC is implemented. Simulation results show a differential nonlinearity (DNL) ranging from −0.23 to 0.101 LSB and an integral nonlinearity (INL) between −0.09 and 0.1723 LSB, which satisfy the specifications for 2-bit resolution at an operating voltage of 1.2 V. The proposed design uses only 15 transistors, significantly fewer than the 48 transistors in comparable designs, demonstrating its suitability for VLSI applications. Moreover, the proposed ADC achieves a power-delay product (PDP) of 0.021 pJ, outperforming existing counterparts. The impact of process, temperature, and supply voltage variations on the proposed method is investigated, and their effects on ADC performance are analyzed. Overall, the results confirm that graphene-MoS2 heterostructures offer a promising platform for scalable and energy-efficient ternary ADC design, contributing to the advancement of atomic-scale nanoelectronic devices.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/7817923","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148381041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Modified Effective Carrier Density in SOI-MESFET With an Asymmetric Dielectric Trapdoor 非对称介质陷门对SOI-MESFET有效载流子密度的影响

IF 1.8 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-07-01 DOI: 10.1049/cds2/7890777

Zohreh Roustaie, Melina Kehtarmanesh, Ali Asghar Orouji

引用次数: 0

Design of Ternary Analog-to-Digital Converter Based on Graphene-MoS2 Heterostructure 基于石墨烯- mos2异质结构的三元模数转换器设计

IF 1.8 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-07-01 DOI: 10.1049/cds2/7817923

Pedram Beyranvand, Behrouz Heidari, Ashkan Horri, Mohammad Bagher Tavakoli

{"title":"Design of Ternary Analog-to-Digital Converter Based on Graphene-MoS2 Heterostructure","authors":"Pedram Beyranvand, Behrouz Heidari, Ashkan Horri, Mohammad Bagher Tavakoli","doi":"10.1049/cds2/7817923","DOIUrl":"10.1049/cds2/7817923","url":null,"abstract":"This paper presents a 2-bit ternary pipelined analog-to-digital converter (ADC) featuring nine quantization levels, implemented using a Dirac source field-effect transistor (DS-FET). The proposed DS-FET is based on graphene-MoS2 heterostructure, that utilizes modulation of the graphene source’s density of states (DOSs) to generate intermediate electronic states. These states enable the realization of three discrete logic levels, which form the foundation of ternary logic operations. By precisely tuning the doping concentration within the graphene source region, the ternary quantizer can be achieved. By using a two-stage pipelined ADC and employing the quantizer in each stage, ternary ADC is implemented. Simulation results show a differential nonlinearity (DNL) ranging from −0.23 to 0.101 LSB and an integral nonlinearity (INL) between −0.09 and 0.1723 LSB, which satisfy the specifications for 2-bit resolution at an operating voltage of 1.2 V. The proposed design uses only 15 transistors, significantly fewer than the 48 transistors in comparable designs, demonstrating its suitability for VLSI applications. Moreover, the proposed ADC achieves a power-delay product (PDP) of 0.021 pJ, outperforming existing counterparts. The impact of process, temperature, and supply voltage variations on the proposed method is investigated, and their effects on ADC performance are analyzed. Overall, the results confirm that graphene-MoS2 heterostructures offer a promising platform for scalable and energy-efficient ternary ADC design, contributing to the advancement of atomic-scale nanoelectronic devices.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/7817923","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148381038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Modified Effective Carrier Density in SOI-MESFET With an Asymmetric Dielectric Trapdoor 非对称介质陷门对SOI-MESFET有效载流子密度的影响

IF 1.8 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-07-01 DOI: 10.1049/cds2/7890777

Zohreh Roustaie, Melina Kehtarmanesh, Ali Asghar Orouji

引用次数: 0

A Comprehensive Review of Fundamental DC/DC Converters: Performance Analysis, Design Considerations, and Applications 基本DC/DC变换器的综合综述：性能分析，设计考虑和应用

IF 1.8 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-06-29 DOI: 10.1049/cds2/9964230

Elias Shokati-Asl, Shanli Samienezhad

{"title":"A Comprehensive Review of Fundamental DC/DC Converters: Performance Analysis, Design Considerations, and Applications","authors":"Elias Shokati-Asl, Shanli Samienezhad","doi":"10.1049/cds2/9964230","DOIUrl":"https://doi.org/10.1049/cds2/9964230","url":null,"abstract":"Nonisolated direct current (DC)–DC converters serve as critical building blocks in modern power management systems. The choice of the optimal topology among numerous options has a direct impact on the efficiency, size, and final cost of the system. This study presents a comprehensive and critical comparative analysis of five fundamental topologies—buck, boost, buck–boost, Ćuk, and SEPIC—in order to provide a clear framework for their selection based on application requirements. The analysis covers the performance of converters in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The evaluation is carried out based on a set of key performance indicators, including critical inductance, output voltage ripple (OVR), voltage and current stresses on switches and diodes, and the continuity nature of input/output current. The results highlight inherent trade-offs among key design parameters of different converter topologies; specifically, fourth-order converters, such as Ćuk and SEPIC, exhibit higher switch voltage stress than buck converters for the same voltage gain, indicating a compromise between improved ripple performance and increased component ratings. Ultimately, this study leads to the presentation of a topology selection guide that enables design engineers to consciously choose the most optimal converter according to specific application requirements, such as the need for low input current ripple or structural simplicity. This work serves as a practical and unified reference for power electronics system designers.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/9964230","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148381180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Mitigating Gate Resistance in 180 nm CMOS High-Frequency LC-VCOs: Enhanced Performance and Simulation-Model Validation 降低180nm CMOS高频lc - vco的栅极电阻：增强性能和仿真模型验证

IF 1.8 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-06-29 DOI: 10.1049/cds2/5399291

Bhanu Teja Pula, Rizwan Shaik Peerla, Arindam Mal, Bibhu Datta Sahoo

引用次数: 0