Iet Circuits Devices & Systems最新文献

{"title":"A Comprehensive Review of Fundamental DC/DC Converters: Performance Analysis, Design Considerations, and Applications","authors":"Elias Shokati-Asl,&nbsp;Shanli Samienezhad","doi":"10.1049/cds2/9964230","DOIUrl":"10.1049/cds2/9964230","url":null,"abstract":"<p>Nonisolated direct current (DC)–DC converters serve as critical building blocks in modern power management systems. The choice of the optimal topology among numerous options has a direct impact on the efficiency, size, and final cost of the system. This study presents a comprehensive and critical comparative analysis of five fundamental topologies—buck, boost, buck–boost, Ćuk, and SEPIC—in order to provide a clear framework for their selection based on application requirements. The analysis covers the performance of converters in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The evaluation is carried out based on a set of key performance indicators, including critical inductance, output voltage ripple (OVR), voltage and current stresses on switches and diodes, and the continuity nature of input/output current. The results highlight inherent trade-offs among key design parameters of different converter topologies; specifically, fourth-order converters, such as Ćuk and SEPIC, exhibit higher switch voltage stress than buck converters for the same voltage gain, indicating a compromise between improved ripple performance and increased component ratings. Ultimately, this study leads to the presentation of a topology selection guide that enables design engineers to consciously choose the most optimal converter according to specific application requirements, such as the need for low input current ripple or structural simplicity. This work serves as a practical and unified reference for power electronics system designers.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/9964230","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148381178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mitigating Gate Resistance in 180 nm CMOS High-Frequency LC-VCOs: Enhanced Performance and Simulation-Model Validation","authors":"Bhanu Teja Pula,&nbsp;Rizwan Shaik Peerla,&nbsp;Arindam Mal,&nbsp;Bibhu Datta Sahoo","doi":"10.1049/cds2/5399291","DOIUrl":"https://doi.org/10.1049/cds2/5399291","url":null,"abstract":"<p>This article presents a detailed analysis of the impact of gate resistance in the inductor-capacitor (LC)-voltage-controlled oscillator (VCO) core. A design guideline centered on the multifinger MOSFET in higher technology nodes (≥90 nm) is proposed to improve the swing and phase noise (PN) of the VCO. As proof of concept, a high-frequency LC-VCO operating from 6.8 to 8.2 GHz using a 5-bit binary-weighted switched capacitor control is realized in UMC 180 nm CMOS. A PN of −108.64 dBc/Hz is achieved at 1 MHz offset for the 7.2 GHz band. The VCO has a tuning range (TR) of 18.66% and a figure-of-merit (FoM) of 177.5 dB, consuming 6.7 mW of power when operating from a 1.8 V supply and occupying a 0.2 mm² area.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/5399291","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148381179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Memristor-Based Logic Circuits: Gate Designs and Cycle-To-Cycle Reliability","authors":"Sridhar Chandrasekaran,&nbsp;Chen Hua,&nbsp;Shan Gao,&nbsp;Guangyu Xue,&nbsp;Jing Wen,&nbsp;Abusaleh Jabir,&nbsp;Dimitra G. Georgiadou,&nbsp;Zohreh Hajiabadi,&nbsp;Zhipeng Liao,&nbsp;Firman M. Simanjuntak","doi":"10.1049/cds2/9915488","DOIUrl":"https://doi.org/10.1049/cds2/9915488","url":null,"abstract":"<p>The implementation of two-terminal memristors could decrease the dependency on the transistors in logic circuits, enabling high-density circuits and reducing power consumption due to the memristor’s smaller feature size and non-volatility, respectively. We propose universal logic function designs based on experimentally acquired electrical characteristics of ZnO-based memristor devices. A highly accurate fitting of set and reset curves is achieved by employing a Verilog model and using it to design primitive gates. OR, NOR, NAND and AND gates can be designed by simply tuning the memristor and pull-up resistor while using a similar circuit configuration. Based on this facile configuration, more complex circuits, such as XOR and XNOR gates, as well as half-adder and half-subtractor combinational logic circuits, can be achieved. Monte Carlo analysis results show that the gates’ output could suffer from a high variation in filament geometry during the cycle-to-cycle switching process, where the variation of the width and height of the filament affects the output significantly, while all gates are tolerant to the variation of the distance between the defects that make up the filament. This work not only highlights the promising alternative design for reconfigurable logical integrated circuits but also addresses the limitations that need to be overcome to design subsystems.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/9915488","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148324404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Memristor-Based Logic Circuits: Gate Designs and Cycle-To-Cycle Reliability","authors":"Sridhar Chandrasekaran,&nbsp;Chen Hua,&nbsp;Shan Gao,&nbsp;Guangyu Xue,&nbsp;Jing Wen,&nbsp;Abusaleh Jabir,&nbsp;Dimitra G. Georgiadou,&nbsp;Zohreh Hajiabadi,&nbsp;Zhipeng Liao,&nbsp;Firman M. Simanjuntak","doi":"10.1049/cds2/9915488","DOIUrl":"https://doi.org/10.1049/cds2/9915488","url":null,"abstract":"<p>The implementation of two-terminal memristors could decrease the dependency on the transistors in logic circuits, enabling high-density circuits and reducing power consumption due to the memristor’s smaller feature size and non-volatility, respectively. We propose universal logic function designs based on experimentally acquired electrical characteristics of ZnO-based memristor devices. A highly accurate fitting of set and reset curves is achieved by employing a Verilog model and using it to design primitive gates. OR, NOR, NAND and AND gates can be designed by simply tuning the memristor and pull-up resistor while using a similar circuit configuration. Based on this facile configuration, more complex circuits, such as XOR and XNOR gates, as well as half-adder and half-subtractor combinational logic circuits, can be achieved. Monte Carlo analysis results show that the gates’ output could suffer from a high variation in filament geometry during the cycle-to-cycle switching process, where the variation of the width and height of the filament affects the output significantly, while all gates are tolerant to the variation of the distance between the defects that make up the filament. This work not only highlights the promising alternative design for reconfigurable logical integrated circuits but also addresses the limitations that need to be overcome to design subsystems.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.8,"publicationDate":"2026-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/9915488","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148324403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of an FPGA-Based Composite Digital Filter for Eliminating ECG Noises","authors":"Suman Saha,&nbsp;Soma Barman Mandal","doi":"10.1049/cds2/4448625","DOIUrl":"https://doi.org/10.1049/cds2/4448625","url":null,"abstract":"<p>The Electrocardiogram (ECG) is a graphical representation of the electrical activity of the heart that is captured through a non-invasive process and is used to monitor the state of the heart. Because of its low power, ECG signal is often contaminated with different types of noises. Noisy ECG recording often leads to misinterpretation of heart disease. Hence, denoising of ECG signal is utmost important for accurate assessment of heart health. Addressing this issue, the paper presents a real-time composite digital filter model that attenuates noise from a corrupted ECG signal. The proposed model integrates three classical digital filters: an elliptic high pass infinite impulse response (IIR) filter, moving average (MA) type finite impulse response (FIR) low pass filter, and IIR elliptic band stop filter. All filters are realized using transposed structure and implemented on FPGA platform. The soft model is developed through graphical programing in MATLAB Simulink by using only basic Xilinx System Generator (XSG) blocks and is emulated in Zedboard Zynq-7000 FPGA board. For hardware emulation of the model, 2.61% of total available resource is utilized and 0.278 W on-chip power is consumed. The Worst Negative Slack (WNS) for our design is 2.789 ns, indicating that it meets all required time constraints and the hardware implementation of the soft design is successful on the FPGA board. The model is tested using 376 ECG recordings from the MIT-BIH Normal Sinus Rhythm, MIT-BIH Arrhythmia, and ECG-ID databases. Additionally, we have introduced various noise signals from the MIT-BIH Noise Stress Test database and synthetically generated in MATLAB to further corrupt the ECG signals. The average improvement in signal-to-noise ratio (SNR_imp) achieved by our model is 7.61 dB for the ECG-ID database, 6.9 dB for the MIT-BIH Arrhythmia database, and 8.42 dB for the MIT-BIH Normal Sinus Rhythm database. The average root mean square error (RMSE) values are 0.0975, 0.2616, and 0.2168, and the average percentage root mean square difference (%PRD) values are 77.91, 64.11, and 68.21 are computed, respectively.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2026-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/4448625","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148237626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of an FPGA-Based Composite Digital Filter for Eliminating ECG Noises","authors":"Suman Saha,&nbsp;Soma Barman Mandal","doi":"10.1049/cds2/4448625","DOIUrl":"https://doi.org/10.1049/cds2/4448625","url":null,"abstract":"<p>The Electrocardiogram (ECG) is a graphical representation of the electrical activity of the heart that is captured through a non-invasive process and is used to monitor the state of the heart. Because of its low power, ECG signal is often contaminated with different types of noises. Noisy ECG recording often leads to misinterpretation of heart disease. Hence, denoising of ECG signal is utmost important for accurate assessment of heart health. Addressing this issue, the paper presents a real-time composite digital filter model that attenuates noise from a corrupted ECG signal. The proposed model integrates three classical digital filters: an elliptic high pass infinite impulse response (IIR) filter, moving average (MA) type finite impulse response (FIR) low pass filter, and IIR elliptic band stop filter. All filters are realized using transposed structure and implemented on FPGA platform. The soft model is developed through graphical programing in MATLAB Simulink by using only basic Xilinx System Generator (XSG) blocks and is emulated in Zedboard Zynq-7000 FPGA board. For hardware emulation of the model, 2.61% of total available resource is utilized and 0.278 W on-chip power is consumed. The Worst Negative Slack (WNS) for our design is 2.789 ns, indicating that it meets all required time constraints and the hardware implementation of the soft design is successful on the FPGA board. The model is tested using 376 ECG recordings from the MIT-BIH Normal Sinus Rhythm, MIT-BIH Arrhythmia, and ECG-ID databases. Additionally, we have introduced various noise signals from the MIT-BIH Noise Stress Test database and synthetically generated in MATLAB to further corrupt the ECG signals. The average improvement in signal-to-noise ratio (SNR_imp) achieved by our model is 7.61 dB for the ECG-ID database, 6.9 dB for the MIT-BIH Arrhythmia database, and 8.42 dB for the MIT-BIH Normal Sinus Rhythm database. The average root mean square error (RMSE) values are 0.0975, 0.2616, and 0.2168, and the average percentage root mean square difference (%PRD) values are 77.91, 64.11, and 68.21 are computed, respectively.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2026-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/4448625","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148237421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Correction to “Fast-Locking Frequency-Hopping PLL Using Dual-Edge Low-Duty-Cycle PFD With Cycle Slip Suppression”","authors":"","doi":"10.1049/cds2/9810389","DOIUrl":"https://doi.org/10.1049/cds2/9810389","url":null,"abstract":"<p>A. Ghaemnia, J. Yang, X. Fei, and G. Zhang, Fast-Locking Frequency-Hopping PLL Using Dual-Edge Low-Duty-Cycle PFD With Cycle Slip Suppression, <i>IET Circuits, Devices &amp; Systems</i>, 2026, 9011136, 15 pages, 2026 https://doi.org/10.1049/cds2/9011136.</p><p>In the Funding section, the text “No funding was received for this manuscript.” was incorrect.</p><p>The correct funding statement is displayed below:</p><p>This work was supported by the Key R&amp;D Program of “Science, Technology and Innovation Yongjiang 2035” (Priority Emergency Project) under Grant No. 20251ZDYF020574.</p><p>We apologize for this error.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2026-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/9810389","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148174237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Correction to “Fast-Locking Frequency-Hopping PLL Using Dual-Edge Low-Duty-Cycle PFD With Cycle Slip Suppression”","authors":"","doi":"10.1049/cds2/9810389","DOIUrl":"https://doi.org/10.1049/cds2/9810389","url":null,"abstract":"<p>A. Ghaemnia, J. Yang, X. Fei, and G. Zhang, Fast-Locking Frequency-Hopping PLL Using Dual-Edge Low-Duty-Cycle PFD With Cycle Slip Suppression, <i>IET Circuits, Devices &amp; Systems</i>, 2026, 9011136, 15 pages, 2026 https://doi.org/10.1049/cds2/9011136.</p><p>In the Funding section, the text “No funding was received for this manuscript.” was incorrect.</p><p>The correct funding statement is displayed below:</p><p>This work was supported by the Key R&amp;D Program of “Science, Technology and Innovation Yongjiang 2035” (Priority Emergency Project) under Grant No. 20251ZDYF020574.</p><p>We apologize for this error.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2026-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/9810389","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148174027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Osmotic Energy Generation in Bioinspired Nanochannels Grafted With Polymer","authors":"Sumit Kumar Mehta,&nbsp;Jinmay Kalita,&nbsp;Pranab Kumar Mondal,&nbsp;Somchai Wongwises","doi":"10.1049/cds2/5551521","DOIUrl":"https://doi.org/10.1049/cds2/5551521","url":null,"abstract":"<p>We investigated osmotic energy generation in a bioinspired nanochannel with grafted polyelectrolyte layer (PEL) by varying the porosity of the PEL. Using finite element based numerical solver, we solved the governing transport equations numerically. In the limiting scenario, we validated our numerical model using theoretical result. We thoroughly studied the cationic concentration field, axial electric field, cationic and anionic current, transference number, net current, diffused potential, maximum power density, and maximum energy conversion efficiency by altering the PEL porosity and the concentration of salt in the left-side reservoir. Together with the changes in reservoir concentration, we found that the PEL porosity significantly influences the axial electric field intensity and cationic concentration field. For the reservoir concentration below the critical limit, it was found that the power density increases with PEL porosity. The highest energy conversion efficiency, on the other hand, was shown to be decreasing as the polyelectrolyte’s porosity increased. The findings of this study contribute to a better understanding of the effects of polyelectrolyte porosity on osmotic energy generation and may aid in the design of high-power density renewable energy generation devices.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2026-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/5551521","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148173873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Osmotic Energy Generation in Bioinspired Nanochannels Grafted With Polymer","authors":"Sumit Kumar Mehta,&nbsp;Jinmay Kalita,&nbsp;Pranab Kumar Mondal,&nbsp;Somchai Wongwises","doi":"10.1049/cds2/5551521","DOIUrl":"https://doi.org/10.1049/cds2/5551521","url":null,"abstract":"<p>We investigated osmotic energy generation in a bioinspired nanochannel with grafted polyelectrolyte layer (PEL) by varying the porosity of the PEL. Using finite element based numerical solver, we solved the governing transport equations numerically. In the limiting scenario, we validated our numerical model using theoretical result. We thoroughly studied the cationic concentration field, axial electric field, cationic and anionic current, transference number, net current, diffused potential, maximum power density, and maximum energy conversion efficiency by altering the PEL porosity and the concentration of salt in the left-side reservoir. Together with the changes in reservoir concentration, we found that the PEL porosity significantly influences the axial electric field intensity and cationic concentration field. For the reservoir concentration below the critical limit, it was found that the power density increases with PEL porosity. The highest energy conversion efficiency, on the other hand, was shown to be decreasing as the polyelectrolyte’s porosity increased. The findings of this study contribute to a better understanding of the effects of polyelectrolyte porosity on osmotic energy generation and may aid in the design of high-power density renewable energy generation devices.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2026-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/5551521","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148173687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}