Iet Circuits Devices & Systems最新文献_第2页

System for PCB Defect Detection Using Visual Computing and Deep Learning for Production Optimization 基于视觉计算和深度学习的PCB缺陷检测系统

4区工程技术

Iet Circuits Devices & Systems Pub Date : 2023-11-03 DOI: 10.1049/2023/6681526

Gabriel Gomes de Oliveira, Gabriel Caumo Vaz, Marcos Antonio Andrade, Yuzo Iano, Leandro Ronchini Ximenes, Rangel Arthur

{"title":"System for PCB Defect Detection Using Visual Computing and Deep Learning for Production Optimization","authors":"Gabriel Gomes de Oliveira, Gabriel Caumo Vaz, Marcos Antonio Andrade, Yuzo Iano, Leandro Ronchini Ximenes, Rangel Arthur","doi":"10.1049/2023/6681526","DOIUrl":"https://doi.org/10.1049/2023/6681526","url":null,"abstract":"With the growing competition between the various manufacturers of electronic products, the quality of the products developed and the consequent confidence in the brand are fundamental factors for the survival of companies. To guarantee the quality of the products in the manufacturing process, it is crucial to identify defects during the production stage of an electronic device. This study presents a system based on traditional visual computing and new deep learning methods to detect defects in electronic devices during the manufacturing process. A prototype of the proposed system was developed and manufactured for direct use in the production line of electronic devices. Tests were performed using a particular smartphone model that had 22 critical components to inspect and the results showed that the proposed system achieved an average accuracy of more than 90% in defect detection when it was directly used in the operational production line. Other studies in this field perform measurements in controlled laboratory environments and identify fewer critical components. Therefore, the proposed method is a real-time high-performance system. Furthermore, the proposed system conforms with the Industry 4.0 goal that process system digitization is essential to improve indicators and optimize production.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"116 S149","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135818373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 7-nm-Based 5R4W High-Timing Reliability Regfile Circuit 一种基于7nm的5R4W高时序可靠性调档电路

4区工程技术

Iet Circuits Devices & Systems Pub Date : 2023-10-31 DOI: 10.1049/2023/1548352

Wanlong Zhao, Yuejun Zhang, Liang Wen, Pengjun Wang

{"title":"A 7-nm-Based 5R4W High-Timing Reliability Regfile Circuit","authors":"Wanlong Zhao, Yuejun Zhang, Liang Wen, Pengjun Wang","doi":"10.1049/2023/1548352","DOIUrl":"https://doi.org/10.1049/2023/1548352","url":null,"abstract":"Register file (Regfile), as the bottleneck circuit for processor data interaction, directly determines the computing performance of the system. To address the read/write conflict and timing error problems of register heap, this paper proposes a 5R4W high-timing reliability Regfile circuit design scheme. First, the scheme analyzed the principles of timing errors such as read/write conflicts, write errors, and read errors in the Regfile circuit; then adopted the timing separation method of independent control of the read/write process by clock double edges to solve multiport read/write conflicts, designed a mirror memory check circuit to avoid write errors caused by the word line delays, and used a phase-locked clock feedback structure to eliminate read errors caused by the data timing fluctuations; in the TSMC 7 nm FinFET process, a 64 × 74-bit 5R4W Regfile circuit was implemented using a fully customized layout. Experimental results show that the Regfile circuit has an area of 0.13 mm2 and consumes 5.541 mW. The circuit operates at a maximum frequency of 3.8 GHz at −40 to −125°C and 0.75 V, and is capable of detecting write errors caused by a clock jitter exceeding 30 ps or a frequency above 5 GHz.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135869961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The Design and Process Reliability Analysis of Millimeter Wave CMOS Power Amplifier with a Cold Mode MOSFET Linearization 冷模MOSFET线性化毫米波CMOS功率放大器设计及工艺可靠性分析

4区工程技术

Iet Circuits Devices & Systems Pub Date : 2023-10-31 DOI: 10.1049/2023/2265697

N. A. Quadir, Amit Jain, S. Kashfi, Lutfi Albasha, Nasser Qaddoumi

引用次数: 0

A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device 一种改善LDMOS器件电学特性的Mini-LOCOS场板廓形工艺优化方法

4区工程技术

Iet Circuits Devices & Systems Pub Date : 2023-10-31 DOI: 10.1049/2023/5298361

Shaoxin Yu, Weiheng Shao, Pei-Xiong Gao, Xiang Li, Rongsheng Chen, Bin Zhao

{"title":"A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device","authors":"Shaoxin Yu, Weiheng Shao, Pei-Xiong Gao, Xiang Li, Rongsheng Chen, Bin Zhao","doi":"10.1049/2023/5298361","DOIUrl":"https://doi.org/10.1049/2023/5298361","url":null,"abstract":"In this work, the effects of the mini-local oxidation of silicon (LOCOS) field plate’s bottom physical profile on the devices’ breakdown performance are analyzed through technology computer-aided design simulations. It is indicated that the “abrupt” bottom profile could certainly do with an optimization. This paper introduces an effective process improvement method by etching bias power adjustment and time reduction. The upgradation of the field plate physical profile has been proved by transmission electron microscope cross-section analysis. The angle for the bottom surface of mini-LOCOS field plate θ2 is improved from 11.9° to 12.6°, and the thickness ratio of Hup/Hbottom (field plate oxide thickness for the upper and bottom, respectively) is increased from 71.8% to 76.6%. Finally, the optimized laterally diffused metal oxide semiconductor devices have been fabricated, and both figure of merit curves and safe operation area curves are measured. The specific on-resistance Ron,sp could achieve as low as 11.3 mΩ mm2, while breakdown voltage BVds,max arrives at 37.4 V, which is nearly 19.3% improved.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"12 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135872636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of Binary and Ternary Logic Inverters Based on Silicon Feedback FETs Using TCAD Simulator 利用TCAD模拟器设计基于硅反馈场效应管的二、三元逻辑逆变器

4区工程技术

Iet Circuits Devices & Systems Pub Date : 2023-10-23 DOI: 10.1049/2023/8833764

Ashkan Horri

{"title":"Design of Binary and Ternary Logic Inverters Based on Silicon Feedback FETs Using TCAD Simulator","authors":"Ashkan Horri","doi":"10.1049/2023/8833764","DOIUrl":"https://doi.org/10.1049/2023/8833764","url":null,"abstract":"A feedback field effect transistor (FBFET) with p-n-p-n structure benefits from a positive feedback mechanism. In this structure, the accumulated charges in its potential well and limitation of carrier flow by its internal potential barrier lead to superior electrical properties such as lower subthreshold swing (SS) and higher <math xmlns=\"http://www.w3.org/1998/Math/MathML\" id=\"M1\"> <msub> <mi>I</mi> <mtext>ON</mtext> </msub> <mo>/</mo> <msub> <mi>I</mi> <mtext>OFF</mtext> </msub> </math> ratio in comparison with FinFET. Thus, FBFET is a promising alternative for digital applications such as logic inverters. In this paper, binary and ternary logic inverters are designed by using FBFETs with 40 nm channel length. The doping profile in the device plays an essential role and specifies the binary or ternary operation of the inverter. The inverter is analyzed by using a TCAD mixed-mode simulator. The results indicate the high value of 1010 for <math xmlns=\"http://www.w3.org/1998/Math/MathML\" id=\"M2\"> <msub> <mi>I</mi> <mtext>ON</mtext> </msub> <mo>/</mo> <msub> <mi>I</mi> <mtext>OFF</mtext> </msub> </math> ratio with an extremely low SS (1 mV/decade). The voltage transfer characteristics of the inverter and its dependence on doping levels have been investigated. Also, the electrical properties of this inverter are compared with previous inverter counterparts.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"47 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135414851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of Low-Cost Full W-Band 8th Harmonic Mixers for Frequency Extension of Spectrum Analyzer 频谱分析仪扩频用低成本全w波段8次谐波混频器的设计

4区工程技术

Iet Circuits Devices & Systems Pub Date : 2023-10-23 DOI: 10.1049/2023/8196039

Jian Guo, Kaiyi Zang, Zihan Zhang, Liang Zhao, Jie Xu, Zhengbin Xu

{"title":"Design of Low-Cost Full W-Band 8th Harmonic Mixers for Frequency Extension of Spectrum Analyzer","authors":"Jian Guo, Kaiyi Zang, Zihan Zhang, Liang Zhao, Jie Xu, Zhengbin Xu","doi":"10.1049/2023/8196039","DOIUrl":"https://doi.org/10.1049/2023/8196039","url":null,"abstract":"High-order harmonic mixer is popular for frequency extension of spectrum analyzer (SA) from microwave to millimeter-wave or even terahertz band. The manufactures of SA usually offer expensive harmonic mixers where frequency extension is needed. In this work, low-cost designs of 2-port and 3-port W-band 8th harmonic mixers covering 75–110 GHz are proposed, and design method of two port mixer without frequency diplexer to separate local oscillator (LO) and intermediate frequency (IF) signals are first presented. These two kinds of mixers are compatible with almost all the current SAs with frequency extension options, which provides LO for the external harmonic mixer. The mixers are designed with planar microstrip lines and antiparallel Schottky diodes. The circuit of 2-port mixer includes the input broadband bandpass filter, diodes, output lowpass filter, and matching circuits. As for 3-port mixer, only an extra diplexer is needed to separate the IF signal and LO signal. The diplexer is composed of a planar semi-lumped lowpass and a highpass filter. The planar circuits are easily fabricated with low-cost print circuit board process on polytetrafluoroethylene substrate. The measured conversion loss of 2-port 8th harmonic mixer is from 20 to 26 dB, and 23 to 28 dB for 3-port mixer at full W-band. The good measured results indicate the proposed mixers are simple and effective.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"44 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135414868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Approach to Increase Power-Added Efficiency in a 5 GHz Class E Power Amplifier in 0.18 µm CMOS Technology 采用0.18µm CMOS技术提高5 GHz E类功率放大器的功率增益效率的方法

4区工程技术

Iet Circuits Devices & Systems Pub Date : 2023-10-23 DOI: 10.1049/2023/5586912

Hemad Heidari Jobaneh

引用次数: 0

Generative Target Tracking Method with Improved Generative Adversarial Network 基于改进生成对抗网络的生成目标跟踪方法

4区工程技术

Iet Circuits Devices & Systems Pub Date : 2023-10-23 DOI: 10.1049/2023/6620581

Yongping Yang, Hongshun Chen

引用次数: 0

Linear broadband interference suppression circuit based on GaN monolithic microwave integrated circuits 基于GaN单片微波集成电路的线性宽带干扰抑制电路

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2023-07-26 DOI: 10.1049/cds2.12159

Megan C. Robinson, Zoya Popović, Gregor Lasser

{"title":"Linear broadband interference suppression circuit based on GaN monolithic microwave integrated circuits","authors":"Megan C. Robinson, Zoya Popović, Gregor Lasser","doi":"10.1049/cds2.12159","DOIUrl":"https://doi.org/10.1049/cds2.12159","url":null,"abstract":"<p>This paper presents simulation and measurement results of a 2–4 GHz octave bandwidth interference suppression circuit. The circuit accomplishes the function of a tunable frequency notch through an interferometer architecture. The relative delay in the interferometer paths is varied with GaN monolithic microwave integrated circuit tunable delay lines. The delay is adjusted by varying the drain voltage of cold-FET connected high electron mobility transistors acting as varactors. Two types of periodically-loaded delay lines are compared: a uniform and a tapered design. A simple theoretical study, relating the delays and amplitudes in the interferometer circuit branches, is developed to inform the design. Two interference suppression hybrid circuits are implemented, and measurements demonstrate a 25–40 dB notch across the 2.24–4 GHz range for the uniform delay line, and 2.32–4.13 GHz for the tapered design. The return loss for both designs remains below 10 dB. Measurements with two tones spaced 0.5 and 1 GHz for varying tone power are performed to quantify suppression. The circuit can handle an input power of 37 dBm and maintains performance with two simultaneous 25 dBm tones spaced 0.5 GHz apart. Linearity is characterised with 10 MHz two-tone measurements, and the circuit demonstrates a 3rd-order intercept input power larger than 30 dBm for control biases above −12 V.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"17 4","pages":"213-224"},"PeriodicalIF":1.3,"publicationDate":"2023-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12159","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50144516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Mechanical model analysis and reliability design approach of Quartz Flexible Accelerometer under fractured state 石英挠性加速度计断裂状态下的力学模型分析及可靠性设计方法

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2023-07-06 DOI: 10.1049/cds2.12161

Tingyu Xiao, Chunxi Zhang, Lailiang Song, Longjun Ran, Wanying Huang

{"title":"Mechanical model analysis and reliability design approach of Quartz Flexible Accelerometer under fractured state","authors":"Tingyu Xiao, Chunxi Zhang, Lailiang Song, Longjun Ran, Wanying Huang","doi":"10.1049/cds2.12161","DOIUrl":"https://doi.org/10.1049/cds2.12161","url":null,"abstract":"<p>Currently, the Quartz Flexible Accelerometer (QFA) mounted for the applications working in high acceleration environment are suffering from the fracture of the flexible beams under external acceleration shock. This paper presents the mechanical model and reliability design approach of QFA to maintain the measuring ability under a fractured state. The structural parameters changed significantly in the mechanical model under a fractured state compared to those in the original model. A modified structure to maintain the measuring ability of QFA under a fractured state is designed with the reference of the sensitive module in Electrostatic Suspended Accelerometer (ESA). The corresponding close-loop system is corrected and discretised to ensure the stability requirements of the mechanical model. A static experiment is conducted to prove the effectiveness of the proposed model by a prototype QFA with completely fractured flexible beams. The result shows helpful on the preliminary research for QFA with the similar sensitive structure to ESA.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"17 4","pages":"225-234"},"PeriodicalIF":1.3,"publicationDate":"2023-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12161","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50122710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0