Iet Circuits Devices & Systems最新文献

{"title":"Optimizing Metro Passenger Flow Prediction: Integrating Machine Learning and Time-Series Analysis with Multimodal Data Fusion","authors":"Li Wan,&nbsp;Wenzhi Cheng,&nbsp;Jie Yang","doi":"10.1049/2024/5259452","DOIUrl":"https://doi.org/10.1049/2024/5259452","url":null,"abstract":"<div>\u0000 <p>Accurate passenger flow forecasting is crucial in urban areas with growing transit demand. In this paper, we propose a method that combines advanced machine learning with rigorous time series analysis to improve prediction accuracy by integrating different datasets, providing a prescriptive example for passenger flow prediction in urban rail transit systems. The study employs advanced machine learning algorithms and proposes a novel prediction model that combines two-stage decomposition (seasonal and trend decomposition using LOESS–ensemble empirical mode decomposition (STL-EEMD)) and gated recurrent units. First, the STL decomposition algorithm is applied to break down the preprocessed data into trend terms, periodic terms, and irregular fluctuation terms. Then, the EEMD decomposition algorithm is employed to further decompose the irregular fluctuation terms, yielding multiple IMF components and residual residuals. Subsequently, the decomposed data from STL and EEMD are partitioned into training and test sets and normalized. The training set is utilized to train the model for optimal performance in predicting subway short-time passenger flow. The synthesis of these sophisticated methodologies serves to substantially enhance both the predictive precision and the broad applicability of the forecasting models. The efficacy of the proposed approach is rigorously evaluated through its application to empirical metro passenger flow datasets from diverse urban centers, demonstrating marked superiority in predictive performance over traditional forecasting methods. The insights gleaned from this study bear significant ramifications for the strategic planning and administration of public transportation infrastructures, potentially leading to more strategic resource allocation and an enhanced commuter experience.</p>\u0000 </div>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2024 1","pages":""},"PeriodicalIF":1.3,"publicationDate":"2024-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/2024/5259452","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141096475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural Network","authors":"Arati Kumari Shah,&nbsp;Kannan Udaya Mohanan,&nbsp;Jisun Park,&nbsp;Hyungsoon Shin,&nbsp;Eou-Sik Cho,&nbsp;Seongjae Cho","doi":"10.1049/2023/1052063","DOIUrl":"10.1049/2023/1052063","url":null,"abstract":"<div>\u0000 <p>Neuron circuits are the fundamental building blocks in the modern neuromorphic system. Designing compact and low-power neuron circuits can significantly improve the overall area and energy efficiencies of a neuromorphic chip architecture. Here, practical neuron circuits must overcome the variations arising from nonideal behaviors of synaptic devices, such as stuck-at-fault and conductance deviation. In this study, a compact leaky integrate-and-fire neuron circuit has been designed, with resilience to synaptic device state variations, for hardware implementation of spiking neural networks (SNNs). The proposed neuron circuit is simulated on the 0.35-<i>μ</i>m Si complementary metal-oxide-semiconductor technology node by a series of circuit simulations based on HSPICE. The proposed circuit occupies a reduced area and exhibits low power consumption (14.7 <i>µ</i>W per spike). Furthermore, the optimized circuit design results in a high degree of tolerance toward input-current variations arising from conductance-state variations in the synapse array. Hence, the proposed neuron circuit would be capable of substantially improving the area efficiency and reliability in the realization of the hardware-oriented SNN architectures.</p>\u0000 </div>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2023 1","pages":""},"PeriodicalIF":1.0,"publicationDate":"2023-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/2023/1052063","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139156089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Implementation of Image Enhancement and Edge Detection Algorithm on Diabetic Retinopathy (DR) Image Using FPGA","authors":"Mumtahina Orthy,&nbsp;Sheikh Md. Rabiul Islam,&nbsp;Faijah Rashid,&nbsp;Md. Asif Hasan","doi":"10.1049/2023/8820773","DOIUrl":"10.1049/2023/8820773","url":null,"abstract":"<div>\u0000 <p>Diabetic retinopathy (DR) is an ocular ailment that may lead to loss of vision and eventual blindness among individuals diagnosed with diabetes. The blood vessels of the retina, a layer of light-sensitive tissue located at the posterior aspect of the ocular globe, are adversely impacted. The identification of DR entails the utilization of retinal fundus images. The detection of any form of abnormality in the eye through raw fundus images poses a significant challenge for medical practitioners. Hence, it is imperative to engage in the processing of fundus images. This paper delineates several image processing techniques for DR images, including but not limited to, manipulation of brightness levels, application of negative transformation, and utilization of threshold operations. It focuses on elucidating the enhancement techniques that pertain to DR images, which aim to optimize the visual quality of said images in order to facilitate more facile disease detection. The process of detecting edges within DR images is also executed by Sobel edge detection algorithm. In order to successfully execute the aforementioned algorithms, expedient and contemporaneous systems are favored to account for the intricacies of the image processing calculations. The exclusive utilization of software techniques in order to fulfill the prerequisites of advanced algorithms presents a significant challenge, owing to the multifarious processes that are involved in their computation, coupled with an exigent requirement for high processing speeds. The proposed model is utilized to articulate a proficient model for the design and execution of field programable gate array (FPGA)-based image enhancement processes along with the Sobel edge detection algorithm upon DR images. Finally, a Internet Protocol chip is developed that can combine multiple image enhancement operations into a single framework with less complexity.</p>\u0000 </div>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2023 1","pages":""},"PeriodicalIF":1.0,"publicationDate":"2023-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/2023/8820773","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139184064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"System for PCB Defect Detection Using Visual Computing and Deep Learning for Production Optimization","authors":"Gabriel Gomes de Oliveira,&nbsp;Gabriel Caumo Vaz,&nbsp;Marcos Antonio Andrade,&nbsp;Yuzo Iano,&nbsp;Leandro Ronchini Ximenes,&nbsp;Rangel Arthur","doi":"10.1049/2023/6681526","DOIUrl":"10.1049/2023/6681526","url":null,"abstract":"<div>\u0000 <p>With the growing competition between the various manufacturers of electronic products, the quality of the products developed and the consequent confidence in the brand are fundamental factors for the survival of companies. To guarantee the quality of the products in the manufacturing process, it is crucial to identify defects during the production stage of an electronic device. This study presents a system based on traditional visual computing and new deep learning methods to detect defects in electronic devices during the manufacturing process. A prototype of the proposed system was developed and manufactured for direct use in the production line of electronic devices. Tests were performed using a particular smartphone model that had 22 critical components to inspect and the results showed that the proposed system achieved an average accuracy of more than 90% in defect detection when it was directly used in the operational production line. Other studies in this field perform measurements in controlled laboratory environments and identify fewer critical components. Therefore, the proposed method is a real-time high-performance system. Furthermore, the proposed system conforms with the Industry 4.0 goal that process system digitization is essential to improve indicators and optimize production.</p>\u0000 </div>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2023 1","pages":""},"PeriodicalIF":1.0,"publicationDate":"2023-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/2023/6681526","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135818373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 7-nm-Based 5R4W High-Timing Reliability Regfile Circuit","authors":"Wanlong Zhao,&nbsp;Yuejun Zhang,&nbsp;Liang Wen,&nbsp;Pengjun Wang","doi":"10.1049/2023/1548352","DOIUrl":"10.1049/2023/1548352","url":null,"abstract":"<div>\u0000 <p>Register file (Regfile), as the bottleneck circuit for processor data interaction, directly determines the computing performance of the system. To address the read/write conflict and timing error problems of register heap, this paper proposes a 5R4W high-timing reliability Regfile circuit design scheme. First, the scheme analyzed the principles of timing errors such as read/write conflicts, write errors, and read errors in the Regfile circuit; then adopted the timing separation method of independent control of the read/write process by clock double edges to solve multiport read/write conflicts, designed a mirror memory check circuit to avoid write errors caused by the word line delays, and used a phase-locked clock feedback structure to eliminate read errors caused by the data timing fluctuations; in the TSMC 7 nm FinFET process, a 64 × 74-bit 5R4W Regfile circuit was implemented using a fully customized layout. Experimental results show that the Regfile circuit has an area of 0.13 mm² and consumes 5.541 mW. The circuit operates at a maximum frequency of 3.8 GHz at −40 to −125°C and 0.75 V, and is capable of detecting write errors caused by a clock jitter exceeding 30 ps or a frequency above 5 GHz.</p>\u0000 </div>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2023 1","pages":""},"PeriodicalIF":1.0,"publicationDate":"2023-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/2023/1548352","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135869961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The Design and Process Reliability Analysis of Millimeter Wave CMOS Power Amplifier with a Cold Mode MOSFET Linearization","authors":"N. A. Quadir,&nbsp;Amit Jain,&nbsp;S. Kashfi,&nbsp;Lutfi Albasha,&nbsp;Nasser Qaddoumi","doi":"10.1049/2023/2265697","DOIUrl":"10.1049/2023/2265697","url":null,"abstract":"<div>\u0000 <p>A power amplifier design operating at 28 GHz for communication applications is presented in this paper. Analog predistorted technique is used to improve the linearity using a cold mode MOSFET linearizer. The paper reports +19.8 dBm of peak power at the output and power-added efficiency (PAE) of 17% is attained by the designed circuit. The 1-dB compression point linearity was +18.6 dBm. The adjacent channel power ratio (ACPR) simulations were performed for the different communication standards like 802_11n_40M, CDMA, IS-95, and 802_11n_20M. Design specification variations of the amplifier have been analyzed over five process corners and simulations were performed to validate compliance with standards and robustness of the designed circuit. Monte Carlo simulation were performed to assess the performance over statistical variability of PAE and power gain. It is believed that this linearization design and the verifications used are done for the first time on a 65-nm RFCMOS process.</p>\u0000 </div>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2023 1","pages":""},"PeriodicalIF":1.0,"publicationDate":"2023-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/2023/2265697","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135872046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device","authors":"Shaoxin Yu,&nbsp;Weiheng Shao,&nbsp;Pei-Xiong Gao,&nbsp;Xiang Li,&nbsp;Rongsheng Chen,&nbsp;Bin Zhao","doi":"10.1049/2023/5298361","DOIUrl":"10.1049/2023/5298361","url":null,"abstract":"<div>\u0000 <p>In this work, the effects of the mini-local oxidation of silicon (LOCOS) field plate’s bottom physical profile on the devices’ breakdown performance are analyzed through technology computer-aided design simulations. It is indicated that the “abrupt” bottom profile could certainly do with an optimization. This paper introduces an effective process improvement method by etching bias power adjustment and time reduction. The upgradation of the field plate physical profile has been proved by transmission electron microscope cross-section analysis. The angle for the bottom surface of mini-LOCOS field plate <i>θ</i>₂ is improved from 11.9° to 12.6°, and the thickness ratio of <i>H</i>_up/<i>H</i>_bottom (field plate oxide thickness for the upper and bottom, respectively) is increased from 71.8% to 76.6%. Finally, the optimized laterally diffused metal oxide semiconductor devices have been fabricated, and both figure of merit curves and safe operation area curves are measured. The specific on-resistance <i>R</i>_on,sp could achieve as low as 11.3 m<i>Ω</i> mm², while breakdown voltage <i>BV</i>_ds,max arrives at 37.4 V, which is nearly 19.3% improved.</p>\u0000 </div>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2023 1","pages":""},"PeriodicalIF":1.0,"publicationDate":"2023-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/2023/5298361","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135872636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of Binary and Ternary Logic Inverters Based on Silicon Feedback FETs Using TCAD Simulator","authors":"Ashkan Horri","doi":"10.1049/2023/8833764","DOIUrl":"10.1049/2023/8833764","url":null,"abstract":"<div>\u0000 <p>A feedback field effect transistor (FBFET) with p-n-p-n structure benefits from a positive feedback mechanism. In this structure, the accumulated charges in its potential well and limitation of carrier flow by its internal potential barrier lead to superior electrical properties such as lower subthreshold swing (SS) and higher <i>I</i>_ON/<i>I</i>_OFF ratio in comparison with FinFET. Thus, FBFET is a promising alternative for digital applications such as logic inverters. In this paper, binary and ternary logic inverters are designed by using FBFETs with 40 nm channel length. The doping profile in the device plays an essential role and specifies the binary or ternary operation of the inverter. The inverter is analyzed by using a TCAD mixed-mode simulator. The results indicate the high value of 10¹⁰ for <i>I</i>_ON/<i>I</i>_OFF ratio with an extremely low SS (1 mV/decade). The voltage transfer characteristics of the inverter and its dependence on doping levels have been investigated. Also, the electrical properties of this inverter are compared with previous inverter counterparts.</p>\u0000 </div>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2023 1","pages":""},"PeriodicalIF":1.0,"publicationDate":"2023-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/2023/8833764","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135414851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of Low-Cost Full W-Band 8th Harmonic Mixers for Frequency Extension of Spectrum Analyzer","authors":"Jian Guo,&nbsp;Kaiyi Zang,&nbsp;Zihan Zhang,&nbsp;Liang Zhao,&nbsp;Jie Xu,&nbsp;Zhengbin Xu","doi":"10.1049/2023/8196039","DOIUrl":"10.1049/2023/8196039","url":null,"abstract":"<div>\u0000 <p>High-order harmonic mixer is popular for frequency extension of spectrum analyzer (SA) from microwave to millimeter-wave or even terahertz band. The manufactures of SA usually offer expensive harmonic mixers where frequency extension is needed. In this work, low-cost designs of 2-port and 3-port W-band 8th harmonic mixers covering 75–110 GHz are proposed, and design method of two port mixer without frequency diplexer to separate local oscillator (LO) and intermediate frequency (IF) signals are first presented. These two kinds of mixers are compatible with almost all the current SAs with frequency extension options, which provides LO for the external harmonic mixer. The mixers are designed with planar microstrip lines and antiparallel Schottky diodes. The circuit of 2-port mixer includes the input broadband bandpass filter, diodes, output lowpass filter, and matching circuits. As for 3-port mixer, only an extra diplexer is needed to separate the IF signal and LO signal. The diplexer is composed of a planar semi-lumped lowpass and a highpass filter. The planar circuits are easily fabricated with low-cost print circuit board process on polytetrafluoroethylene substrate. The measured conversion loss of 2-port 8th harmonic mixer is from 20 to 26 dB, and 23 to 28 dB for 3-port mixer at full W-band. The good measured results indicate the proposed mixers are simple and effective.</p>\u0000 </div>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2023 1","pages":""},"PeriodicalIF":1.0,"publicationDate":"2023-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/2023/8196039","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135414868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Approach to Increase Power-Added Efficiency in a 5 GHz Class E Power Amplifier in 0.18 µm CMOS Technology","authors":"Hemad Heidari Jobaneh","doi":"10.1049/2023/5586912","DOIUrl":"10.1049/2023/5586912","url":null,"abstract":"<div>\u0000 <p>A new approach to increasing the power-added efficiency (PAE) of a class E power amplifier (PA) is proposed in this paper. The PA operates at a 5 GHz frequency and a reactance compensation technique is utilized to maximize the bandwidth at the operating frequency. The driver stage creates either a half-wave rectified sine wave or a half-wave rectified sawtooth wave. By applying each one of the waves, the performance of the PA is examined and PAE = 70% and PAE = 50% is achieved. Plus, the output power of the PA is about 26 dBm when the DC voltage supply is 1.8 V. Advanced design system and TSMC 0.18 <i>µ</i>m CMOS process are utilized to carry on the simulation.</p>\u0000 </div>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2023 1","pages":""},"PeriodicalIF":1.0,"publicationDate":"2023-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/2023/5586912","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135414552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}