冷模MOSFET线性化毫米波CMOS功率放大器设计及工艺可靠性分析

IF 1 4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Iet Circuits Devices & Systems Pub Date : 2023-10-31 DOI:10.1049/2023/2265697

N. A. Quadir, Amit Jain, S. Kashfi, Lutfi Albasha, Nasser Qaddoumi

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引用次数: 0

摘要

本文介绍了一种用于通信应用的28ghz功率放大器的设计。采用模拟预失真技术，利用冷模MOSFET线性化器改善线性度。该电路的输出峰值功率为+19.8 dBm，功率附加效率(PAE)为17%。1db压缩点线性度为+18.6 dBm。对802_11n_40M、CDMA、IS-95和802_11n_20M等不同通信标准进行了相邻信道功率比(ACPR)仿真。分析了放大器在五个工艺角上的设计规范变化，并进行了仿真，以验证所设计电路的符合标准和鲁棒性。通过蒙特卡罗模拟来评估PAE和功率增益的统计变异性的性能。据信，这种线性化设计和所使用的验证是首次在65纳米RFCMOS工艺上完成的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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The Design and Process Reliability Analysis of Millimeter Wave CMOS Power Amplifier with a Cold Mode MOSFET Linearization

A power amplifier design operating at 28 GHz for communication applications is presented in this paper. Analog predistorted technique is used to improve the linearity using a cold mode MOSFET linearizer. The paper reports +19.8 dBm of peak power at the output and power-added efficiency (PAE) of 17% is attained by the designed circuit. The 1-dB compression point linearity was +18.6 dBm. The adjacent channel power ratio (ACPR) simulations were performed for the different communication standards like 802_11n_40M, CDMA, IS-95, and 802_11n_20M. Design specification variations of the amplifier have been analyzed over five process corners and simulations were performed to validate compliance with standards and robustness of the designed circuit. Monte Carlo simulation were performed to assess the performance over statistical variability of PAE and power gain. It is believed that this linearization design and the verifications used are done for the first time on a 65-nm RFCMOS process.

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来源期刊

Iet Circuits Devices & Systems 工程技术-工程：电子与电气

CiteScore

3.80

自引率

7.70%

发文量

审稿时长

3 months

期刊介绍： IET Circuits, Devices & Systems covers the following topics: Circuit theory and design, circuit analysis and simulation, computer aided design Filters (analogue and switched capacitor) Circuit implementations, cells and architectures for integration including VLSI Testability, fault tolerant design, minimisation of circuits and CAD for VLSI Novel or improved electronic devices for both traditional and emerging technologies including nanoelectronics and MEMs Device and process characterisation, device parameter extraction schemes Mathematics of circuits and systems theory Test and measurement techniques involving electronic circuits, circuits for industrial applications, sensors and transducers