Iet Circuits Devices & Systems最新文献_第3页

High-Efficiency Cascaded Step-Up DC–DC Converter With Passive Clamping and Voltage Multiplication 具有无源箝位和倍增电压的高效级联升压DC-DC变换器

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-05-11 DOI: 10.1049/cds2/1401230

Farzad Mohammadzadeh Shahir, Navid Hadifar

{"title":"High-Efficiency Cascaded Step-Up DC–DC Converter With Passive Clamping and Voltage Multiplication","authors":"Farzad Mohammadzadeh Shahir, Navid Hadifar","doi":"10.1049/cds2/1401230","DOIUrl":"https://doi.org/10.1049/cds2/1401230","url":null,"abstract":"This article presents a novel hybrid coupled-inductor (CI) cascaded high step-up (HCICHSU) DC–DC converter tailored for renewable energy systems. The proposed converter achieves ultrahigh voltage gain, low voltage stress on semiconductor devices, and continuous input current by combining buck–boost and boost topologies within a hybrid cascaded structure. The topology targets large conversion at a moderate duty cycle while keeping device stresses low and maintaining a smooth input current. Continuous-conduction operation is analyzed, and expressions for voltage gain, device stresses, and component sizing are derived. A loss model and sensitivity discussion identify dominant loss mechanisms at high conversion ratios. For control, a small-signal model is developed, and the inherent right-half-plane zero (RHPZ) is handled using a Type-III compensator. Experimental verification uses a 160 W prototype stepping 24 to 200 V. The converter reaches 94.4% efficiency at full load and limits drain-to-source peak voltages to about 48 and 60 V for the two main switches, confirming effective leakage-energy recovery and stress reduction in practice. Measured waveforms show stable regulation and consistent currents.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2026-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/1401230","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148073079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-05-11

引用次数: 0

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-05-11

引用次数: 0

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-05-04

引用次数: 0

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-05-04

引用次数: 0

Cost-Effective Winner-Take-All Approach for Comparing Multi-Output Neural Networks 比较多输出神经网络的成本效益赢家通吃方法

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-05-04 DOI: 10.1049/cds2/7326994

Saleh Abdel-Hafeez, Samer Abubaker

{"title":"Cost-Effective Winner-Take-All Approach for Comparing Multi-Output Neural Networks","authors":"Saleh Abdel-Hafeez, Samer Abubaker","doi":"10.1049/cds2/7326994","DOIUrl":"https://doi.org/10.1049/cds2/7326994","url":null,"abstract":"This work focuses on designing a winner-take-all (WTA) algorithm using digital circuits, rather than the more commonly used analog circuits. In this context, neurons are represented as digital bits, similar to those in convolutional neural networks (CNNs) and weightless neural networks (WNNs). The proposed WTA circuit compares the most significant bits (MSBs) of all neurons (or discriminators) in parallel. The results of this initial comparison are then used to evaluate the second MSBs, where a parallel comparison is performed. This process continues iteratively for each subsequent bit until the least significant bits (LSBs) are analyzed. By removing less significant neurons early in the process, the number of signals that switch activity in subsequent comparisons is decreased, thereby reducing overall dynamic power. The WTA circuit consists of an array of OR–AND configurations that employ low-cost CMOS logic gates and operate without a clock or any form of synchronization. This design inherits the advantages of scalability and configurability: adding a new neuron requires only inserting a new row of cells, while increasing the size of the neurons can be accomplished by adding new columns of cells. The design characteristics rely on two factors: the number of neurons (K) and the size of each neuron (N bits). Neuron size plays a crucial role in determining the critical path delay.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2026-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/7326994","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148065586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimized Hybrid Deep Learning-Based FPGA Accelerators for Denoising of Ultrasound Breast Images 基于FPGA的超声乳腺图像去噪优化混合深度学习加速器

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-04-28 DOI: 10.1049/cds2/8273657

K. Janaki, Usha Moorthy, K. Kausalya, R. Jennie Bharathi

{"title":"Optimized Hybrid Deep Learning-Based FPGA Accelerators for Denoising of Ultrasound Breast Images","authors":"K. Janaki, Usha Moorthy, K. Kausalya, R. Jennie Bharathi","doi":"10.1049/cds2/8273657","DOIUrl":"https://doi.org/10.1049/cds2/8273657","url":null,"abstract":"This paper introduces a novel image-denoising technique that integrates a hybrid deep learning (DL) model with a self-improved orca predation (SOP) strategy. This hybrid model improves denoising performance by integrating a Convolutional Neural Network (CNN) with Bidirectional Long Short-Term Memory (Bi-LSTM). The hybrid model’s hyperparameters are enhanced using the SOP technique, resulting in superior denoising outcomes. The proposed approach is experimentally tested with the INbreast and CBIS-DDSM datasets. The results demonstrate that the suggested method outperforms conventional approaches, making it a viable option for image-denoising applications. The suggested technique achieved a PSNR of 35.905 on the INbreast dataset and 37.08 on the CBIS-DDSM dataset. However, the DL model demands a significant amount of memory and computing capacity, limiting its implementation on edge devices and causing computing delays and energy loss. Field Programmable Gate Arrays (FPGAs) are ideal for practical applications due to their high computational capability and low power consumption. In this paper, we implement the proposed model on a ZCU104 FPGA board, evaluate its performance, and analyze resource utilization. The experimental outcome shows that the proposed network on the chosen FPGA achieves an impressive execution time of 4.25 s, low power consumption of 3.2 W, and a throughput of 47 images per second.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2026-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/8273657","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148096839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-04-28

引用次数: 0

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-04-28

引用次数: 0

Fast-Locking Frequency-Hopping PLL Using Dual-Edge Low-Duty-Cycle PFD With Cycle Slip Suppression 采用带周跳抑制的双边低占空比PFD的快速锁定跳频锁相环

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2026-03-30 DOI: 10.1049/cds2/9011136

Afifeh Ghaemnia, Jincheng Yang, Xiaojiong Fei, Guoqiang Zhang

{"title":"Fast-Locking Frequency-Hopping PLL Using Dual-Edge Low-Duty-Cycle PFD With Cycle Slip Suppression","authors":"Afifeh Ghaemnia, Jincheng Yang, Xiaojiong Fei, Guoqiang Zhang","doi":"10.1049/cds2/9011136","DOIUrl":"10.1049/cds2/9011136","url":null,"abstract":"The performance of conventional phase–frequency detectors (PFDs) is critically limited by dead-zone and blind-zone artifacts, which stem from the timing constraints of D flip-flop (DFF) based architectures. These non-idealities degrade phase-detection resolution, induce cycle slip, and prolong the lock time of phase-locked loops (PLLs). This paper introduces a dual-edge low-duty-cycle PFD (DELD–PFD) that utilizes high-speed feed-through and output-prediction logic flip-flops to detect both rising and falling edges of the input clocks, thereby eliminating the dead and blind zones and enhancing phase resolution. The proposed architecture inherently generates low-duty-cycle output pulses, which reduces charge-pump current mismatch and improves loop dynamics. Fabricated in a standard 55 nm CMOS technology, the post-layout simulation results validate operation across 1 MHz–5.5 GHz. The DELD–PFD achieves a lock-time reduction of 63% relative to a conventional PLL, consumes 74 µW at 5 GHz from a 1.2 V supply, and delivers a phase noise of –147 dBc/Hz at a 1 MHz offset. Comprehensive Monte Carlo and PVT (process, voltage, and temperature) simulations confirm robustness across variations, demonstrating the design’s suitability for high-speed, low-noise, frequency-hopping PLL applications.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2026 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2026-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/9011136","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147668937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0