Iet Circuits Devices & Systems最新文献

{"title":"Quasi-fixed frequency controlled phase modulation LCC resonant converter with a wide power range","authors":"Ying Feng,&nbsp;Dejun Kong","doi":"10.1049/cds2.12155","DOIUrl":"https://doi.org/10.1049/cds2.12155","url":null,"abstract":"<p>The research on LCC resonant converters has become increasingly popular since the application of the zero-voltage switching can improve the transmission ability and ensure the high efficiency of the power supplies. In this article, a novel quasi-definite frequency-based modulation control method to extend the excellent properties of LCC resonators to a wide range of powers is introduced. By adjusting the frequency and phase in a bidirectional manner in accordance with the design law, excellent output performance can be maintained over a wide power range, which is overcome by adjusting the switching frequency and phase separately in conventional modulation methods. In order to justify the effectiveness of the proposed modulation control method, a simulation and experimental platform of LCC resonators using the proposed modulation method was performed. Simulation and experimental results can effectively demonstrate the performance of the proposed modulation control method for a variety of input voltage and output power cases, and the efficiency of the LCC converters will be improved in higher power systems.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"17 3","pages":"160-173"},"PeriodicalIF":1.3,"publicationDate":"2023-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12155","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50118974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Construction of visual evaluation system for building block night scene lighting based on multi-target recognition and data processing","authors":"Xiaojian Wang,&nbsp;Xiaoye Sun,&nbsp;Zixuan Wang","doi":"10.1049/cds2.12154","DOIUrl":"https://doi.org/10.1049/cds2.12154","url":null,"abstract":"<p>The rapid development of night tourism economy has made people's demand for night scene lighting in architectural blocks increasing, and the night scene lighting situation of urban architectural blocks has gradually received people's attention and attention. Achieving good night lighting visual effects of building blocks can not only meet the needs of residents for entertainment and consumption at night, but also beautify the image of blocks and promote the economic development of building blocks. However, due to the unreasonable planning and management of the night scene lighting design of architectural blocks in some areas, improper application of night scene lighting, and overly commercial night scene lighting effects, it affects people's normal night activity needs and has a negative impact on the long-term block economy of the region. Faced with this situation, the night lighting of architectural blocks and its problems is studied and photos are identified with high lighting visual effect evaluation using multi-target identification and data processing to construct a night lighting visual evaluation system for architectural blocks, and also an experimental study of the visual evaluation system is conducted. The results show that the overall visual suitability evaluation support rate of the respondents for the night scene lighting of architectural blocks is 95.64%, and the visual evaluation system proposed in this paper is reasonable and effective, which is conducive to promoting the improvement of the visual effect of night scene lighting in architectural blocks.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"17 3","pages":"149-159"},"PeriodicalIF":1.3,"publicationDate":"2023-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12154","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50149389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comprehensive survey of ternary full adders: Statistics, corrections, and assessments","authors":"Sarina Nemati,&nbsp;Mostafa Haghi Kashani,&nbsp;Reza Faghih Mirzaee","doi":"10.1049/cds2.12152","DOIUrl":"https://doi.org/10.1049/cds2.12152","url":null,"abstract":"<p>The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This article conducts a review of TFAs so that one can be familiar with the utilised design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0 V or V_DD. This way, in a single-V_DD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this favourable condition in the literature. Additionally, most of the simulation setups in the previous articles are not realistic enough. Therefore, the simulation results reported in these papers are neither comparable nor entirely valid. Therefore, the authors got motivated to conduct a survey, elaborate on this issue, and enhance some of the previous designs. Among 84 papers, 10 different TFAs (from 11 papers) are selected, simplified, and simulated in this article. Simulation results by HSPICE and 32 nm carbon nanotube FET technology reveal that the simplified partial TFAs outperform their original versions in terms of delay, power, and transistor count.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"17 3","pages":"111-134"},"PeriodicalIF":1.3,"publicationDate":"2023-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12152","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50132344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 128 Gbps PAM-4 feed forward equaliser with optimized 1UI pulse generator in 65 nm CMOS","authors":"Jiawei Wang,&nbsp;Hao Xu,&nbsp;Ziqiang Wang,&nbsp;Haikun Jia,&nbsp;Hanjun Jiang,&nbsp;Chun Zhang,&nbsp;Zhihua Wang","doi":"10.1049/cds2.12151","DOIUrl":"https://doi.org/10.1049/cds2.12151","url":null,"abstract":"<p>A quarter-rate PAM-4 FFE employing INCC 1UIPG is implemented in 65 nm CMOS. The proposed INNC 1UIPG reduces the average transition time by ~20%, saving clocking power consumption by ~1.5X, lowering jitter amplification by about 2~5 dB compared with previous works. Along with the bandwidth- and power-efficient partially segmented tailless 1-stage front-end architecture, the proposed FFE achieves 128Gbps PAM-4 data rate with a 0.014 mm² area.\u0000 <figure>\u0000 <div><picture>\u0000 <source></source></picture><p></p>\u0000 </div>\u0000 </figure></p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"17 3","pages":"174-179"},"PeriodicalIF":1.3,"publicationDate":"2023-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12151","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50139373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A combined capacitor current balancing method with weighting factor control for multi-string LED drivers","authors":"Hajar Sedghi,&nbsp;Mohammad Sarvi","doi":"10.1049/cds2.12145","DOIUrl":"https://doi.org/10.1049/cds2.12145","url":null,"abstract":"<p>A multi-string LED lamp driver is presented involving a boost converter and a multi-output CLL resonant converter as the first and second stages, respectively. The CLL resonant converter works in a fixed resonant frequency, and output currents are controlled by the boost converter regulated by the Weighting Factor control method. Also, the boost converter improves and controls its input voltage. Since CLL resonant converters operate at fixed resonant frequency, primary-side MOSFETs can achieve zero voltage switching, while secondary-side rectifier diodes achieve zero current switching. A prototype of the proposed system was constructed to verify the theoretical results by practical implementation. Also, the general features of the proposed structure were compared with some other similar works. Results confirmed the accuracy and favourable performance of the proposed system. In fact, the proposed LED driver achieved good current balancing in a wide range of input voltage and unbalanced loads making the structure potentially suitable for application in solar home systems (SHS).</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"17 3","pages":"135-148"},"PeriodicalIF":1.3,"publicationDate":"2023-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12145","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50120596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Retracted: Multi-mode urban rail transit and spatial coordinated development based on deep learning system","authors":"Xiaojian Wang,&nbsp;Zixuan Wang,&nbsp;Xiaoye Sun","doi":"10.1049/cds2.12144","DOIUrl":"https://doi.org/10.1049/cds2.12144","url":null,"abstract":"<p>Retraction: [Xiaojian Wang, Zixuan Wang, Xiaoye Sun, Multi-mode urban rail transit and spatial coordinated development based on deep learning system, <i>IET Circuits, Devices &amp; Systems</i> 2023 (https://doi.org/10.1049/cds2.12144)].</p><p>The above article from <i>IET Circuits, Devices &amp; Systems</i>, published online on 10 January 2023 in Wiley Online Library (wileyonlinelibrary.com), has been retracted by agreement between the Editor-in-Chief, Harry E. Ruda, the Institution of Engineering and Technology (the IET) and John Wiley and Sons Ltd. This article was published as part of a Guest Edited special issue. Following an investigation, the IET and the journal have determined that the article was not reviewed in line with the journal’s peer review standards and there is evidence that the peer revie process of the special issue underwent systematic manipulation. Accordingly, we cannot vouch for the integrity or reliability of the content. As such we have taken the decision to retract the article. The authors have been informed of the decision to retract.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"17 4","pages":"291-300"},"PeriodicalIF":1.3,"publicationDate":"2023-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12144","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50127535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A PVT resilient true-time delay cell","authors":"Ahmad Yarahmadi,&nbsp;Abumoslem Jannesari","doi":"10.1049/cds2.12143","DOIUrl":"https://doi.org/10.1049/cds2.12143","url":null,"abstract":"<p>A true-time delay (TTD) cell in TSMC 0.18 μm CMOS technology for 1–5 GHz applications is presented. Process variations, ageing effects, field variations, and other non-idealities have some impacts on the TTD cell's devices. One of the vulnerable specifications of TTD cells is their delay variation. While the TTD cell works in a delay line, the cell must have a constant and robust delay in the frequency band. For this matter, the body bias technique is presented and applied to the inductor-less TTD cell. With this technique, the threshold voltage can be manipulated intentionally. So, any variation in this voltage can be compensated with the body biasing of transistors. The simulation results show the TTD cell's robust performance against non-idealities, while delay variation improves more than 3× times in the frequency band of interest. This TTD cell provides a 50.95 pS delay with only 2% variation, while S₁₁ and S₂₂ parameters are lower than −10 dB in the 1–5 GHz frequency band. IIP3 of the TTD cell is about 2.7 dBm, and the power consumption is 20.5 mW.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"17 2","pages":"95-110"},"PeriodicalIF":1.3,"publicationDate":"2023-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12143","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50146407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 1.0 fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process","authors":"Chua-Chin Wang,&nbsp;Ralph Gerard B. Sangalang,&nbsp;I-Ting Tseng,&nbsp;Yi-Jen Chiu,&nbsp;Yu-Cheng Lin,&nbsp;Oliver Lexter July A. Jose","doi":"10.1049/cds2.12141","DOIUrl":"https://doi.org/10.1049/cds2.12141","url":null,"abstract":"<p>An ultra-low-energy SRAM composed of single-ended cells is demonstrated on silicon in this investigation. More specifically, the supply voltages of cells are gated by wordline (WL) enable, and the voltage mode select (VMS) signals select one of the corresponding supply voltages. A lower voltage is selected to maintain stored bit state when cells are not accessed, lowering the standby power. And when selecting a cell (i.e. WL is enabled) to perform the read or write (R/W) operations, the normal supply voltage is used. A 1-kb SRAM prototype based on the single-ended cells with built-in self-test (BIST) and power-delay production (PDP) reduction circuits was realised on silicon using 40-nm CMOS technology. Theoretical derivations and simulations of all-PVT-corner variations are also disclosed to justify low energy performance. Physical measurements of six prototypes on silicon shows that the energy per bit is 1.0 fJ at the 10 MHz system clock.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"17 2","pages":"75-87"},"PeriodicalIF":1.3,"publicationDate":"2023-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12141","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50146406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A new method for calculation of closed-form response of linear time-invariant systems to periodic input signals","authors":"Ahmad Safaai-Jazi","doi":"10.1049/cds2.12142","DOIUrl":"https://doi.org/10.1049/cds2.12142","url":null,"abstract":"&lt;p&gt;A new method for finding closed-form time-domain solutions of linear time-invariant (LTI) systems with arbitrary periodic input signals is presented. These solutions, unlike those obtained based on the conventional Fourier-phasor method, have a finite number of terms in one period. To implement the proposed method, the following steps are carried out: (1) For a given system, represented by a transfer function, an impulse response, a block diagram etc., the governing differential equation relating the output of the system, &lt;math&gt;\u0000 &lt;semantics&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mi&gt;y&lt;/mi&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mo&gt;(&lt;/mo&gt;\u0000 &lt;mi&gt;t&lt;/mi&gt;\u0000 &lt;mo&gt;)&lt;/mo&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;annotation&gt; $y(t)$&lt;/annotation&gt;\u0000 &lt;/semantics&gt;&lt;/math&gt;, to its input, &lt;math&gt;\u0000 &lt;semantics&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mi&gt;x&lt;/mi&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mo&gt;(&lt;/mo&gt;\u0000 &lt;mi&gt;t&lt;/mi&gt;\u0000 &lt;mo&gt;)&lt;/mo&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;annotation&gt; $x(t)$&lt;/annotation&gt;\u0000 &lt;/semantics&gt;&lt;/math&gt;, is obtained. (2) An auxiliary differential equation is formed by simply replacing &lt;math&gt;\u0000 &lt;semantics&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mi&gt;y&lt;/mi&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mo&gt;(&lt;/mo&gt;\u0000 &lt;mi&gt;t&lt;/mi&gt;\u0000 &lt;mo&gt;)&lt;/mo&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;annotation&gt; $y(t)$&lt;/annotation&gt;\u0000 &lt;/semantics&gt;&lt;/math&gt; with &lt;math&gt;\u0000 &lt;semantics&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mover&gt;\u0000 &lt;mi&gt;y&lt;/mi&gt;\u0000 &lt;mo&gt;‾&lt;/mo&gt;\u0000 &lt;/mover&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mo&gt;(&lt;/mo&gt;\u0000 &lt;mi&gt;t&lt;/mi&gt;\u0000 &lt;mo&gt;)&lt;/mo&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;annotation&gt; $overline{y}(t)$&lt;/annotation&gt;\u0000 &lt;/semantics&gt;&lt;/math&gt; and equating the input side to&lt;math&gt;\u0000 &lt;semantics&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mi&gt;x&lt;/mi&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mo&gt;(&lt;/mo&gt;\u0000 &lt;mi&gt;t&lt;/mi&gt;\u0000 &lt;mo&gt;)&lt;/mo&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;/mrow&gt;\u0000 &lt;annotation&gt; $x(t)$&lt;/annotation&gt;\u0000 &lt;/semantics&gt;&lt;/math&gt; alone. The auxiliary differential equation is solved for each time segment of the input signal in one period, leaving the constant coefficients associated with the homogeneous solutions as unknowns. For an &lt;i&gt;n&lt;/i&gt;th-order system with an input signal consisting of &lt;i&gt;q&lt;/i&gt; segments in one period, there are &lt;math&gt;\u0000 &lt;semantics&gt;\u0000 &lt;mrow&gt;\u0000 &lt;mi&gt;n&lt;/mi&gt;\u0000 ","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"17 2","pages":"88-94"},"PeriodicalIF":1.3,"publicationDate":"2023-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12142","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50120207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Retracted: Multi-vehicle group-aware data protection model based on differential privacy for autonomous sensor networks","authors":"Jiazheng Yuan,&nbsp;Zhuang Wang,&nbsp;Cheng Xu,&nbsp;Hongtian Li,&nbsp;Songyin Dai,&nbsp;Hongzhe Liu","doi":"10.1049/cds2.12140","DOIUrl":"https://doi.org/10.1049/cds2.12140","url":null,"abstract":"<p>Retraction: [Jiazheng Yuan, Zhuang Wang, Cheng Xu, Hongtian Li, Songyin Dai, Hongzhe Liu, Multi-vehicle group-aware data protection model based on differential privacy for autonomous sensor networks, <i>IET Circuits, Devices &amp; Systems</i> 2022 (https://doi.org/10.1049/cds2.12140)].</p><p>The above article from <i>IET Circuits, Devices &amp; Systems</i>, published online on 29 December 2022 in Wiley Online Library (wileyonlinelibrary.com), has been retracted by agreement between the Editor-in-Chief, Harry E. Ruda, the Institution of Engineering and Technology (the IET) and John Wiley and Sons Ltd. This article was published as part of a Guest Edited special issue. Following an investigation, the IET and the journal have determined that the article was not reviewed in line with the journal's peer review standards and there is evidence that the peer revie process of the special issue underwent systematic manipulation. Accordingly, we cannot vouch for the integrity or reliability of the content. As such we have taken the decision to retract the article. The authors have been informed of the decision to retract.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"17 4","pages":"278-290"},"PeriodicalIF":1.3,"publicationDate":"2022-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12140","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50147455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}