宽带高动态范围模数转换器的硬件原型

IF 1 4区 工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC
Satish Mulleti, Eliya Reznitskiy, Shlomi Savariego, Moshe Namer, Nimrod Glazer, Yonina C. Eldar
{"title":"宽带高动态范围模数转换器的硬件原型","authors":"Satish Mulleti,&nbsp;Eliya Reznitskiy,&nbsp;Shlomi Savariego,&nbsp;Moshe Namer,&nbsp;Nimrod Glazer,&nbsp;Yonina C. Eldar","doi":"10.1049/cds2.12156","DOIUrl":null,"url":null,"abstract":"<p>Key parameters of analog-to-digital converters (ADCs) are their sampling rate and dynamic range. Power consumption and cost of an ADC are directly proportional to the sampling rate; hence, it is desirable to keep it as low as possible. The dynamic range of an ADC also plays an important role, and ideally, it should be greater than the signal's; otherwise, the signal will be clipped. To avoid clipping, modulo folding can be used before sampling, followed by an unfolding algorithm to recover the true signal. Here, the authors present a modulo hardware prototype that can be used before sampling to avoid clipping. The authors’ modulo hardware operates prior to the sampling mechanism and can fold higher frequency signals compared to existing hardware. The authors present a detailed design of the hardware and also address key issues that arise during implementation. In terms of applications, the authors show the reconstruction of finite-rate-of-innovation signals, which are beyond the dynamic range of the ADC. The authors’ system operates at six times below the Nyquist rate of the signal and can accommodate eight times larger signals than the ADC's dynamic range.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"17 4","pages":"181-192"},"PeriodicalIF":1.0000,"publicationDate":"2023-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12156","citationCount":"1","resultStr":"{\"title\":\"A hardware prototype of wideband high-dynamic range analog-to-digital converter\",\"authors\":\"Satish Mulleti,&nbsp;Eliya Reznitskiy,&nbsp;Shlomi Savariego,&nbsp;Moshe Namer,&nbsp;Nimrod Glazer,&nbsp;Yonina C. Eldar\",\"doi\":\"10.1049/cds2.12156\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<p>Key parameters of analog-to-digital converters (ADCs) are their sampling rate and dynamic range. Power consumption and cost of an ADC are directly proportional to the sampling rate; hence, it is desirable to keep it as low as possible. The dynamic range of an ADC also plays an important role, and ideally, it should be greater than the signal's; otherwise, the signal will be clipped. To avoid clipping, modulo folding can be used before sampling, followed by an unfolding algorithm to recover the true signal. Here, the authors present a modulo hardware prototype that can be used before sampling to avoid clipping. The authors’ modulo hardware operates prior to the sampling mechanism and can fold higher frequency signals compared to existing hardware. The authors present a detailed design of the hardware and also address key issues that arise during implementation. In terms of applications, the authors show the reconstruction of finite-rate-of-innovation signals, which are beyond the dynamic range of the ADC. The authors’ system operates at six times below the Nyquist rate of the signal and can accommodate eight times larger signals than the ADC's dynamic range.</p>\",\"PeriodicalId\":50386,\"journal\":{\"name\":\"Iet Circuits Devices & Systems\",\"volume\":\"17 4\",\"pages\":\"181-192\"},\"PeriodicalIF\":1.0000,\"publicationDate\":\"2023-06-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12156\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Iet Circuits Devices & Systems\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://onlinelibrary.wiley.com/doi/10.1049/cds2.12156\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Iet Circuits Devices & Systems","FirstCategoryId":"5","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1049/cds2.12156","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 1

摘要

模数转换器(ADC)的关键参数是其采样率和动态范围。ADC的功耗和成本与采样率成正比;因此,希望将其保持在尽可能低的水平。ADC的动态范围也起着重要作用,理想情况下,它应该大于信号的动态范围;否则,信号将被削波。为了避免削波,可以在采样前使用模折叠,然后使用展开算法来恢复真实信号。在这里,作者提出了一个模硬件原型,可以在采样前使用,以避免剪裁。作者的模硬件在采样机制之前操作,与现有硬件相比,可以折叠更高频率的信号。作者介绍了硬件的详细设计,并解决了实现过程中出现的关键问题。在应用方面,作者展示了有限创新率信号的重建,这些信号超出了ADC的动态范围。作者的系统以比信号的奈奎斯特速率低六倍的速率工作,并且可以容纳比ADC的动态范围大八倍的信号。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

A hardware prototype of wideband high-dynamic range analog-to-digital converter

A hardware prototype of wideband high-dynamic range analog-to-digital converter

Key parameters of analog-to-digital converters (ADCs) are their sampling rate and dynamic range. Power consumption and cost of an ADC are directly proportional to the sampling rate; hence, it is desirable to keep it as low as possible. The dynamic range of an ADC also plays an important role, and ideally, it should be greater than the signal's; otherwise, the signal will be clipped. To avoid clipping, modulo folding can be used before sampling, followed by an unfolding algorithm to recover the true signal. Here, the authors present a modulo hardware prototype that can be used before sampling to avoid clipping. The authors’ modulo hardware operates prior to the sampling mechanism and can fold higher frequency signals compared to existing hardware. The authors present a detailed design of the hardware and also address key issues that arise during implementation. In terms of applications, the authors show the reconstruction of finite-rate-of-innovation signals, which are beyond the dynamic range of the ADC. The authors’ system operates at six times below the Nyquist rate of the signal and can accommodate eight times larger signals than the ADC's dynamic range.

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来源期刊
Iet Circuits Devices & Systems
Iet Circuits Devices & Systems 工程技术-工程:电子与电气
CiteScore
3.80
自引率
7.70%
发文量
32
审稿时长
3 months
期刊介绍: IET Circuits, Devices & Systems covers the following topics: Circuit theory and design, circuit analysis and simulation, computer aided design Filters (analogue and switched capacitor) Circuit implementations, cells and architectures for integration including VLSI Testability, fault tolerant design, minimisation of circuits and CAD for VLSI Novel or improved electronic devices for both traditional and emerging technologies including nanoelectronics and MEMs Device and process characterisation, device parameter extraction schemes Mathematics of circuits and systems theory Test and measurement techniques involving electronic circuits, circuits for industrial applications, sensors and transducers
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