A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device

IF 1 4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Iet Circuits Devices & Systems Pub Date : 2023-10-31 DOI:10.1049/2023/5298361

Shaoxin Yu, Weiheng Shao, Pei-Xiong Gao, Xiang Li, Rongsheng Chen, Bin Zhao

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Abstract

In this work, the effects of the mini-local oxidation of silicon (LOCOS) field plate’s bottom physical profile on the devices’ breakdown performance are analyzed through technology computer-aided design simulations. It is indicated that the “abrupt” bottom profile could certainly do with an optimization. This paper introduces an effective process improvement method by etching bias power adjustment and time reduction. The upgradation of the field plate physical profile has been proved by transmission electron microscope cross-section analysis. The angle for the bottom surface of mini-LOCOS field plate θ2 is improved from 11.9° to 12.6°, and the thickness ratio of Hup/Hbottom (field plate oxide thickness for the upper and bottom, respectively) is increased from 71.8% to 76.6%. Finally, the optimized laterally diffused metal oxide semiconductor devices have been fabricated, and both figure of merit curves and safe operation area curves are measured. The specific on-resistance Ron,sp could achieve as low as 11.3 mΩ mm2, while breakdown voltage BVds,max arrives at 37.4 V, which is nearly 19.3% improved.

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一种改善LDMOS器件电学特性的Mini-LOCOS场板廓形工艺优化方法

本文通过计算机辅助设计模拟技术，分析了硅微局部氧化(LOCOS)场极板底部物理剖面对器件击穿性能的影响。指出“突兀”的底部轮廓肯定可以进行优化。本文介绍了一种有效的工艺改进方法，即蚀刻偏压功率调整和时间缩短。通过透射电镜的截面分析，证明了场板物理剖面的改进。mini-LOCOS场板θ2底表面角度由11.9°提高到12.6°，上、底场板氧化层厚度Hup/Hbottom比由71.8%提高到76.6%。最后，制作了优化后的横向扩散金属氧化物半导体器件，并测量了性能曲线和安全操作面积曲线。比导通电阻Ron,sp可低至11.3 mΩ mm2，击穿电压BVds,max可达37.4 V，提高近19.3%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Iet Circuits Devices & Systems 工程技术-工程：电子与电气

CiteScore

3.80

自引率

7.70%

发文量

审稿时长

3 months

期刊介绍： IET Circuits, Devices & Systems covers the following topics: Circuit theory and design, circuit analysis and simulation, computer aided design Filters (analogue and switched capacitor) Circuit implementations, cells and architectures for integration including VLSI Testability, fault tolerant design, minimisation of circuits and CAD for VLSI Novel or improved electronic devices for both traditional and emerging technologies including nanoelectronics and MEMs Device and process characterisation, device parameter extraction schemes Mathematics of circuits and systems theory Test and measurement techniques involving electronic circuits, circuits for industrial applications, sensors and transducers