Iet Circuits Devices & Systems最新文献_第9页

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-11-20

引用次数: 0

A High-Efficiency CNN Accelerator With Mixed Low-Precision Quantization 混合低精度量化的高效CNN加速器

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-11-20 DOI: 10.1049/cds2/5433740

Xianghong Hu, Jinhui Pan, Yue Ding, Wenji Huang, Zhejun Zheng, Xueming Li, Hongmin Huang, Xiaoming Xiong

{"title":"A High-Efficiency CNN Accelerator With Mixed Low-Precision Quantization","authors":"Xianghong Hu, Jinhui Pan, Yue Ding, Wenji Huang, Zhejun Zheng, Xueming Li, Hongmin Huang, Xiaoming Xiong","doi":"10.1049/cds2/5433740","DOIUrl":"10.1049/cds2/5433740","url":null,"abstract":"In the field of hardware accelerators for convolutional neural network (CNN) inference, quantization techniques have been widely employed to enhance the performance. The prevailing quantization scheme of the accelerator at present is using signed 8-bit integer variables (INT8). CNN accelerators support INT8, while lower precision INT4 is less common. Accelerators supporting INT4 depthwise separable convolution (DWC) are even rarer. Therefore, this article presents a high-performance CNN accelerator that not only supports 8-bit and 4-bit data but also supports standard convolution (SC) and DWC. Additionally, in order to improve the transmission efficiency of DWC, an intermediate cache strategy is proposed, using a pointwise convolution (PW) input buffer (PW BUF) to store output data from depthwise convolution (DW) to avoid off-chip transmission. Furthermore, to address the issue of a DSP cannot perform two 4 × 4-bit multiplications when dealing with DW, a processing element (PE) is designed to make full use of DSP hardware resources. Finally, this accelerator is implemented on ZYNQ ZC706 with a frequency of 200 MHz. Experimental results show that it achieves a performance up to 307.88 giga operations per second (GOPS) on VGG, reaching 97.9% peak performance; while on MobileNet, it achieves efficient performance with 206.43 GOPS with only 392 DSPs. Compared with mainstream CNN accelerators, it increases DSP utilization rate (GOPS/DSP) by 1.5× to 33.5×.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/5433740","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145581105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-11-18

引用次数: 0

Challenges in Modelling Analog PUFs: A Study of Hybrid and Diode Triode Current Mirror Inverter PUF Under Machine Learning Attacks 模拟PUF建模的挑战：机器学习攻击下混合和二极管三极管电流镜逆变器PUF的研究

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-11-18 DOI: 10.1049/cds2/3903508

Gisha Chittattukara Girijan, Ananda Sankar Chakraborty, Rajat Subhra Chakraborty, Bijoy Antony Jose, Jimson Mathew

{"title":"Challenges in Modelling Analog PUFs: A Study of Hybrid and Diode Triode Current Mirror Inverter PUF Under Machine Learning Attacks","authors":"Gisha Chittattukara Girijan, Ananda Sankar Chakraborty, Rajat Subhra Chakraborty, Bijoy Antony Jose, Jimson Mathew","doi":"10.1049/cds2/3903508","DOIUrl":"10.1049/cds2/3903508","url":null,"abstract":"Physically unclonable function-based authentication is one of the widely accepted and promising hardware security primitives. For security applications, strong PUF circuits can generate a large number of challenge–response pairs (CRPs) for authentication. These CRPs can, however, be utilised by machine learning (ML) techniques to model the physically unclonable function (PUF) and forecast its responses. In this paper, we evaluate the robustness of analog PUF designs, specifically hybrid current mirror inverter (HCMI) and diode triode current mirror inverter (DTCMI) PUFs, against ML attacks. The XOR-tree configuration in the PUF amplifies entropy and introduces additional nonlinearity, making the CRP mapping significantly harder to model. Deep neural networks (DNNs) attack and the PyPUF toolbox were utilised to evaluate the modelling attacks on the HCMI and DTCMI PUFs. Experiments were conducted using CRP counts ranging from 10,000 to 1,000,000. Despite varying the number of hidden layers and nodes in the DNN model, the attack accuracy consistently remained near 50%, indicating the robustness of analog PUFs to ML-based modelling techniques. The evaluation using the PyPUF toolbox also resulted in consistent accuracy near 50%, indicating poor learnability. The results highlight the strong resistance of XOR-tree-enhanced HCMI and DTCMI analog PUF designs to advanced machine-learning attacks compared to the vulnerabilities of conventional digital PUFs.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/3903508","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145572229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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A Time Domain ISFET With Dynamic Reference Switching 具有动态参考开关的时域ISFET

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-11-15 DOI: 10.1049/cds2/9569273

Jose Cortes Guzman, Pablo G. Ledesma Lopez, Andreas Tsiamis, David R. S. Cummings, Srinjoy Mitra

{"title":"A Time Domain ISFET With Dynamic Reference Switching","authors":"Jose Cortes Guzman, Pablo G. Ledesma Lopez, Andreas Tsiamis, David R. S. Cummings, Srinjoy Mitra","doi":"10.1049/cds2/9569273","DOIUrl":"10.1049/cds2/9569273","url":null,"abstract":"This paper presents an enhanced linear pulse-frequency modulator (LPFM) ion-sensitive field-effect transistor (ISFET) architecture with a programmable dynamic range for pH detection. The circuit encodes the pH signal into the frequency domain. This proposed method is shown to have higher stability for supply variation. A dynamic referencing scheme is used to increase the stability of the recording over long periods. The circuit’s operating point and dynamic range can be programmed, enhancing the versatility of the architecture. The design was implemented in a 0.18 µm standard CMOS process, with a sensing area as an extended gate electrode of 125 µm × 125 µm. The architecture was electrically and electrochemically characterised. The ISFET chip was post-processed by thinning the passivation layer over the sensing area. The results showed a boost in the sensitivity of 230%, an increase of 9% in the passivation capacitance with an intact SiO2 layer, and a 45% reduction of the Si3N4 layer. Compared to a rapid decay in signal quality, the dynamic reference method showed consistent measurements over hours. The circuit also showed very low sensitivity for around 25% supply variation.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/9569273","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145522148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-11-15

引用次数: 0

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-10-31

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An FFT Optimal Scaling Vector Search Scheme Based on Dynamic Programming 一种基于动态规划的FFT最优缩放向量搜索方案

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-10-31 DOI: 10.1049/cds2/5773930

Jinwei Xie, Yubin Zhu, Kaining Han, Jianhao Hu

{"title":"An FFT Optimal Scaling Vector Search Scheme Based on Dynamic Programming","authors":"Jinwei Xie, Yubin Zhu, Kaining Han, Jianhao Hu","doi":"10.1049/cds2/5773930","DOIUrl":"10.1049/cds2/5773930","url":null,"abstract":"The fast Fourier transform (FFT) is widely used in digital signal processing. However, hardware implementations of the discrete Fourier transform (DFT)/FFT are limited by word length constraints, necessitating truncation, saturation, and scaling operations to balance hardware resources and computational performance. The choice of a suitable scaling vector significantly affects FFT efficiency. This paper introduces a novel estimation model for FFT error power, accounting for both quantization and saturation errors. Based on this model, we propose a dynamic programming (DP)-based scaling vector search scheme to reduce the search space and computational complexity. After 1000 experiments, the model demonstrated a mean and variance of relative error in signal-to-noise ratio (SNR) of 0.063 and 0.35, proving its effectiveness. In a case study of a 1024-point FFT, our model accurately estimated error power. While the exhaustive search yielded an optimal SNR of 65.91 dB, our method reduced the search space by 3600 times, with only a 0.3 dB loss in SNR. In a 256-point FFT hardware implementation, performance improved by over 10 dB. Our scheme achieves SNR performance comparable to other methods when bit width is fixed and superior SNR when bit width is variable. This approach offers guidance for selecting scaling vectors in FFT hardware design.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/5773930","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145407010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-10-31

引用次数: 0

Bayesian-Optimization-Based Post-Silicon Offset-Cancelation Technique for Analog Multipliers 基于贝叶斯优化的模拟乘法器后硅偏移抵消技术

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-10-31 DOI: 10.1049/cds2/5591883

Thisara Kulatunga, Svetlana Yanushkevich, Leonid Belostotski

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