Iet Circuits Devices & Systems最新文献_第9页

Delayered IC image analysis with template-based Tanimoto Convolution and Morphological Decision 基于模板的谷本卷积和形态学决策的延迟IC图像分析

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-08-03 DOI: 10.1049/cds2.12093

Deruo Cheng, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee, Kar-Ann Toh

{"title":"Delayered IC image analysis with template-based Tanimoto Convolution and Morphological Decision","authors":"Deruo Cheng, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee, Kar-Ann Toh","doi":"10.1049/cds2.12093","DOIUrl":"10.1049/cds2.12093","url":null,"abstract":"Supervised machine learning techniques are being pursued for delayered Integrated Circuit (IC) image analysis. However, repetitive data labelling and model training are required for every image set with the supervised techniques. In view of the large scale of IC image set being analysed, techniques that require less human intervention are desired. In this paper, we propose a template-based Tanimoto Convolution and Morphological Decision (TCMD) model for transistor interconnection retrieval in delayered ICs, that is, poly line segmentation, with minimal human intervention. In our proposed TCMD model, prior domain knowledge on the IC images is incorporated into the proposed Tanimoto convolution for generating input feature maps, eliminating the need of filter learning. We further propose morphological decision to process the input feature maps for higher accuracy and robustness on determining poly line positions. With experiments on a delayered IC @90 nm process, our proposed TCMD model achieves 3%∼6% higher accuracy than the reported template-based techniques. Our proposed TCMD model also achieves competitive accuracy with the reported deep U-net while requiring 13× shorter training/validation time. To further improve the pixel-wise precision of the retrieved poly lines, which is important for applications such as analog circuit analysis, we propose a deep learning-based TCMD-PL model. The proposed TCMD-PL model utilises the output of TCMD model as the pseudo labels for training a deep convolutional neural network in supervised manner, and it is able to achieve further performance improvement of ∼4% in comparison to TCMD model without extra data labelling.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 2","pages":"169-177"},"PeriodicalIF":1.3,"publicationDate":"2021-08-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12093","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125680594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Current-voltage model of a graphene nanoribbon p-n junction and Schottky junction diode 石墨烯纳米带pn结和肖特基结二极管的电流-电压模型

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-07-30 DOI: 10.1049/cds2.12092

Samira Shamsir, Laila Parvin Poly, Rajat Chakraborty, Samia Subrina

{"title":"Current-voltage model of a graphene nanoribbon p-n junction and Schottky junction diode","authors":"Samira Shamsir, Laila Parvin Poly, Rajat Chakraborty, Samia Subrina","doi":"10.1049/cds2.12092","DOIUrl":"10.1049/cds2.12092","url":null,"abstract":"This work presents a simplified analytical model of a p-n junction diode based on a graphene nanoribbon (GNR) and a unique type of Schottky diode based on metallic graphene and semi-conducting GNRs. Due to the one-dimensional nature of GNRs, their electrostatic analyses need to be quite different from that of bulk devices. Two approaches have been taken to model the charge distribution in this depletion region, namely, the point charge approximation for the GNR p-n junction diode and the line charge approximation for the graphene/GNR Schottky diode. Analytical expressions for the spatial distribution of electric field and potential have been derived and the results are quite distinct from their bulk counterparts. The current-voltage relation of each diode has been investigated within the approximation of Shockley's law of junctions. The width dependency of the currents for these diodes has also been modelled and it has been found that the current density of both the diodes decreases with decreasing width. Such an analysis can encourage the modelling of next-generation GNR-based high-speed electronic devices.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 2","pages":"157-168"},"PeriodicalIF":1.3,"publicationDate":"2021-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12092","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114647404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

An efficient loop tiling framework for convolutional neural network inference accelerators 卷积神经网络推理加速器的高效循环平铺框架

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-07-20 DOI: 10.1049/cds2.12091

Hongmin Huang, Xianghong Hu, Xueming Li, Xiaoming Xiong

{"title":"An efficient loop tiling framework for convolutional neural network inference accelerators","authors":"Hongmin Huang, Xianghong Hu, Xueming Li, Xiaoming Xiong","doi":"10.1049/cds2.12091","DOIUrl":"10.1049/cds2.12091","url":null,"abstract":"Convolutional neural networks (CNNs) have been widely applied in the field of computer vision due to their inherent advantages in image feature extraction. However, it is difficult to implement CNNs directly on embedded platforms owing to excessive calculations of CNNs. Field Programmable Gate Arrays have been popular in CNN accelerators because of their configurability and high energy efficiency. Given the highly parallel workloads of the CNN, a CNN accelerator with a 14 × 16 processing element array is designed in this study to accelerate the CNN inference. Besides, a loop tiling strategy for convolutional layers is proposed to efficiently transmit feature maps. Additionally, the roofline model is employed to explore the best tiling parameters for optimal performance. Finally, the accelerator written in Verilog-HDL language is implemented on the Xilinx Zynq-7045 evaluation platform. At an operating frequency of 200 MHz, the proposed accelerator can achieve a performance of 57.24 giga operations per second on You Only Look Once v2-tiny and 78.39 GOPS on Visual Geometry Group-16. The accelerator only consumes 224 DSPs, demonstrating a better performance compared with the previous works.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 1","pages":"116-123"},"PeriodicalIF":1.3,"publicationDate":"2021-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12091","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117310869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Effect analysis of adding selective experiments in power electronics course to encourage students’ active learning 电力电子学课程中增加选择性实验，鼓励学生主动学习的效果分析

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-07-14 DOI: 10.1049/cds2.12090

Guopeng Zhao

{"title":"Effect analysis of adding selective experiments in power electronics course to encourage students’ active learning","authors":"Guopeng Zhao","doi":"10.1049/cds2.12090","DOIUrl":"10.1049/cds2.12090","url":null,"abstract":"In order to meet the need for more experimental content for students with strong active learning ability and to solve the problem of students’ different needs for experimental content and depth, a teaching method of adding selective experiments is proposed in this study on the basis of basic experiments. The method is also aimed at achieving the need for multi-level teaching. In the experimental course, the teacher arranges all the students in the class and makes them perform the basic circuit experiment. The teacher then adds the selective experiments on the basis of the basic experimental circuit so that the students can freely select the experiment they want to complete and meet the need for expanding the experimental needs of students with strong active learning ability. In this study, the voltage regulating circuit experiment is taken as an example to carry out practical teaching. The basic experimental content is a single-phase voltage regulating circuit experiment, and the selective experiment is a three-phase voltage regulating circuit experiment. The final examination scores of the students who have performed the selective experiments are higher than the average score of the class, which shows that the students who have performed the selective experiments are good students with a strong need for active learning. The curriculum of this study meets their need for active learning. With the help of the realisation rate of the circuit function, the correct answer rate of thinking questions and the experimental time of students who have performed the selective experiments, it is shown that the method of multi-level teaching and differentiated experimental teaching is feasible. Through the questionnaire survey of students, it can be seen that the teaching method proposed in this study can meet the students’ need for active learning, improve students’ interest in the course, and increase the opportunities for training students’ practical ability.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 2","pages":"147-156"},"PeriodicalIF":1.3,"publicationDate":"2021-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12090","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115525978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A new soft-switching high step-down DC-DC converter for voltage regular module application 一种适用于电压规则模块的新型软开关高降压DC-DC变换器

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-07-09 DOI: 10.1049/cds2.12089

Mahmood Vesali, Hosein Ranjbar, Farhad Ghafoorian

引用次数: 6

Blinding HT: Hiding Hardware Trojan signals traced across multiple sequential levels 盲HT:隐藏硬件木马信号跟踪跨多个顺序级别

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-06-25 DOI: 10.1049/cds2.12088

Ying Zhang, Minghui Ge, Xin Chen, Jiaqi Yao, Zhiming Mao

{"title":"Blinding HT: Hiding Hardware Trojan signals traced across multiple sequential levels","authors":"Ying Zhang, Minghui Ge, Xin Chen, Jiaqi Yao, Zhiming Mao","doi":"10.1049/cds2.12088","DOIUrl":"10.1049/cds2.12088","url":null,"abstract":"Modern electronic systems usually use third-party IP cores to build basic blocks. However, there may be Hardware Trojans (HTs) in IP cores, which will cause critical security problem. There are already many HT detection methods which claim to detect all publicly available HT benchmarks. But these methods can still be defeated by designing novel HTs. In this article, a method called Blinding HT is proposed, which camouflages itself as a normal circuit and is difficult to be triggered. The Blinding HT hides input signals of HT modules by tracing across multiple sequential levels. This method increases the influence of HT trigger inputs on output signals, so that trigger inputs are not be identified as redundant inputs. In this way, this approach can defeat the detection methods which identify weakly affecting trigger inputs and redundant trigger inputs across multiple sequential levels. As shown in the experimental results, the proposed HTs are hardly detected even by the novel HT detection approach based on machine learning algorithm. These HTs have small footprints on the design in terms of area and power to resist the side-channel effect analysis. The proposed HT has stealthiness, general applicability and imperceptibility.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 1","pages":"105-115"},"PeriodicalIF":1.3,"publicationDate":"2021-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12088","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121712654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of a 128-channel transceiver hardware for medical ultrasound imaging systems 用于医学超声成像系统的128通道收发器硬件设计

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-06-17 DOI: 10.1049/cds2.12087

Jayaraj Kidav, Perumal M. Pillai, Deepak V, Sreejeesh S. G

{"title":"Design of a 128-channel transceiver hardware for medical ultrasound imaging systems","authors":"Jayaraj Kidav, Perumal M. Pillai, Deepak V, Sreejeesh S. G","doi":"10.1049/cds2.12087","DOIUrl":"10.1049/cds2.12087","url":null,"abstract":"In this work, the design and development of a 128-channel transceiver hardware for medical ultrasound imaging systems and research is presented. The proposed hardware solution integrates the analog front-end (AFE) sections, high voltage transmit pulser sections, field programmable gate array (FPGA)-based transmit beamforming and control logic, time gain compensation (TGC) and continuous (CW) Doppler functional circuits, and the necessary power supplies (high voltage (HV) and low voltage (LV)) into a single board. In addition, it integrates pervasive segments like power, clock tree sections, and power management and debugger logic. The developed transceiver solution helps to advance the research in medical ultrasound imaging techniques and technologies. To prototype an ultrasound imaging system, the developed hardware can be interfaced with a 128-channel ultrasound transducer array and an FPGA-based signal processing module. As the transceiver hardware is designed with commercially available chipsets, it provides the flexibility to programme the ultrasound AFE signal chain, transmit beamforming and the arbitrary transmit wave pattern. Besides, compared to the commercial open ultrasound research scanners, the flexibility to interface FPGA-based signal processing module helps to investigate the performance of hardware realisation of various ultrasound signal processing algorithms. Moreover, the work realises a single-board transceiver solution for multichannel ultrasound system fulfilment.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 1","pages":"92-104"},"PeriodicalIF":1.3,"publicationDate":"2021-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12087","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132669132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Spice modelling of a tri-state memristor and analysis of its series and parallel characteristics 三态记忆电阻器的Spice建模及其串联和并联特性分析

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-05-30 DOI: 10.1049/cds2.12086

Pu Li, Xiaoyuan Wang, Xue Zhang, Jason K. Eshraghian, Herbert Ho Ching Lu

{"title":"Spice modelling of a tri-state memristor and analysis of its series and parallel characteristics","authors":"Pu Li, Xiaoyuan Wang, Xue Zhang, Jason K. Eshraghian, Herbert Ho Ching Lu","doi":"10.1049/cds2.12086","DOIUrl":"10.1049/cds2.12086","url":null,"abstract":"Memristors are passive non-linear circuit components with memory characteristics, and have been recognized as the fourth basic circuit component, along with resistors, capacitors, and inductors. It has been nearly half a century since the conceptualisation of the memristor, and related research has mainly focussed on the two aspects of binary and continuous memristors. However, compared with these two types of memristors, tri-state and multi-state memristors have greater data density per device, with rich dynamics and great potential in logic and chaotic circuit applications. Moreover, previous studies show that the series-parallel connection of memristor generates more diverse circuit behaviours and increased capacity over a single memristor. However, most of this research is based on mathematical analysis, and lack behavioural circuit simulations or experimental validation. Here, the tri-state memristor is proposed and the mathematic and equivalent Spice models of the tri-state memristor is shown. Furthermore, the circuit characteristics are studied with a complete characterisation of its series-parallel behaviours of the tri-state memristor. Simulations are performed with LTSpice, and the results verify the theoretical analysis, which provides a strong experimental basis for the study of combinational memristive circuits.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 1","pages":"81-91"},"PeriodicalIF":1.3,"publicationDate":"2021-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12086","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128438175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

CORRIGENDUM Systematic Cell placement in Quantum-dot Cellular Automata Embedding Underlying Regular Clocking Circuit 在量子点细胞自动机中嵌入规则时钟电路的系统细胞放置

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-05-25 DOI: 10.1049/cds2.12082

引用次数: 0

A new coplanar design of a 4-bit ripple carry adder based on quantum-dot cellular automata technology 基于量子点元胞自动机技术的4位纹波进位加法器共面设计

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-05-24 DOI: 10.1049/cds2.12083

Saeid Seyedi, Behrouz Pourghebleh, Nima Jafari Navimipour

{"title":"A new coplanar design of a 4-bit ripple carry adder based on quantum-dot cellular automata technology","authors":"Saeid Seyedi, Behrouz Pourghebleh, Nima Jafari Navimipour","doi":"10.1049/cds2.12083","DOIUrl":"10.1049/cds2.12083","url":null,"abstract":"Quantum-dot cellular automata (QCA) is one of the best methods to implement digital circuits at nanoscale. It has excellent potential with high density, fast switching speed, and low energy consumption. Researchers have emphasized reducing the number of gates, the delay, and the cell count in QCA technology. In addition, a ripple carry adder (RCA) is a circuit in which each full adder's carry-out is the connection for the next full adder's carry-in. These types of adders are quite simple and easily expandable to any desired size. However, they are relatively slow because carries may broadcast across the entire adder. Therefore, an RCA design on a nanoscale QCA is proposed to diminish the cell number, improve complexity, and decrease latency. The QCADesigner simulation tool is used to verify the correctness of the suggested circuit. The comparison results for the design indicate an approximately 49.14% improvement in cell number and 14.29% advantage in area for the state-of-the-art 4-bit RCA designs with QCA technology. In addition, the obtained results specify the effectiveness of the offered design.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 1","pages":"64-70"},"PeriodicalIF":1.3,"publicationDate":"2021-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12083","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122614378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14