Iet Circuits Devices & Systems最新文献_第9页

A transformer-less DC–DC converter with high voltage conversion ratio adopting inverting voltage lift cell 一种采用逆变升压单元的无变压器高电压变换器

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-11-03 DOI: 10.1049/cds2.12101

Ebrahim Babaei, Hamed Mashinchi Maheri, Mehran Sabahi

引用次数: 2

Effect of adding small applications after verification experiment in a power electronics course 在电力电子学课程中加入验证实验后的小应用效果

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-09-19 DOI: 10.1049/cds2.12099

Guopeng Zhao

{"title":"Effect of adding small applications after verification experiment in a power electronics course","authors":"Guopeng Zhao","doi":"10.1049/cds2.12099","DOIUrl":"10.1049/cds2.12099","url":null,"abstract":"In order to deepen the understanding of power electronics circuits, in this study, a teaching method of adding simple small applications of circuits on the basis of basic verification experiments is proposed. Teachers teach basic principles and applications of circuits, and students conduct basic verification experiments of circuits in the laboratory. Simple application experiments are added after the verification experiments. The full-bridge DC-DC converter circuit is taken as an example to carry out practical teaching. After completing the function of the full-bridge DC-DC converter circuit, a load of DC motor is used. The full-bridge DC-DC converter circuit is used to control the speed of the DC motor so as to realise the simple application of the full-bridge DC-DC converter circuit with a motor speed control function. By comparing the experimental realisation rate, the correct rate of thinking questions and the in-depth understanding of the application theory of two experimental classes, namely the class with simple applications and the class without simple applications, it is shown that the students with simple application experiments improved the correct rate of thinking questions and deepened their understanding of the applications. Compared with the situation in which most students in the class that did not conduct the application experiment did not know the application principle in detail, most students in the class that conducted the application experiment had a deep understanding of the applications. Through the questionnaire survey of students, it is observed that the method proposed in this study could deepen the understanding of circuits and the students had a simple and preliminary understanding of the applications of power electronics technology. It improved students' interest in the course and their practicing ability. The proposed teaching method had a good effect.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 3","pages":"218-227"},"PeriodicalIF":1.3,"publicationDate":"2021-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12099","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122565574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Thermal field reconstruction based on weighted dictionary learning 基于加权字典学习的热场重构

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-09-16 DOI: 10.1049/cds2.12098

Tianyi Zhang, Wenchang Li, Jinyu Xiao, Jian Liu

{"title":"Thermal field reconstruction based on weighted dictionary learning","authors":"Tianyi Zhang, Wenchang Li, Jinyu Xiao, Jian Liu","doi":"10.1049/cds2.12098","DOIUrl":"10.1049/cds2.12098","url":null,"abstract":"Dynamic thermal management (DTM) is applied to address the thermal problem of high performance very-large-scale integrated chips. The false alarm rate (FAR) can be used to evaluate the impact of full-chip thermal field reconstruction accuracy on DTM. A low FAR relies on the accurate reconstruction of the full thermal field, especially near the temperature triggering threshold of DTM. However, little attention is currently being paid to such temperature ranges. To reduce FAR, a new full-chip thermal field reconstruction strategy is proposed. A low-dimensional linear model is used to accurately represent the thermal fields. The dictionary learning technology is exploited to train the model and the minimum weighted mean square error evaluation method is incorporated to improve the reconstruction accuracy near the temperature triggering threshold. A temperature sensor placement algorithm using the heuristic algorithm to solve the NP-hard problem is also proposed. The experimental results show that the proposed strategy can reconstruct the full thermal field with a more precise accuracy near the triggering threshold and achieve the lowest FAR compared to the state of the art.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 3","pages":"228-239"},"PeriodicalIF":1.3,"publicationDate":"2021-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12098","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130224761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A high-performance full swing 1-bit hybrid full adder cell 高性能全摆位1位混合全加法器单元

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-09-04 DOI: 10.1049/cds2.12097

Shahbaz Hussain, Mehedi Hasan, Gazal Agrawal, Mohd Hasan

引用次数: 15

Theoretical total harmonic distortion evaluation based on digital to analogue converter mismatch to improve the linearity of successive approximation register analogue to digital converter 基于数模转换器失配的理论总谐波失真评估，以提高逐次逼近寄存器模拟数字转换器的线性度

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-09-04 DOI: 10.1049/cds2.12095

Li Dong, Yan Song, Bing Zhang, Zhechong Lan, Youze Xin, Liheng Liu, Ken Li, Xiaofei Wang, Li Geng

{"title":"Theoretical total harmonic distortion evaluation based on digital to analogue converter mismatch to improve the linearity of successive approximation register analogue to digital converter","authors":"Li Dong, Yan Song, Bing Zhang, Zhechong Lan, Youze Xin, Liheng Liu, Ken Li, Xiaofei Wang, Li Geng","doi":"10.1049/cds2.12095","DOIUrl":"10.1049/cds2.12095","url":null,"abstract":"Mismatch in the binary-weighted capacitive digital-to-analog converter (DAC) greatly affects the linearity of the successive-approximation-register (SAR) ADC by deteriorating the total harmonic distortion (THD). In this study, a theoretical relationship between the THD and the mismatch error of DAC array in SAR ADC is derived through discrete Fourier transform (DFT) analysis of the time-based integral error (TIE) of the ADC's output codes, which has no specific requirement on the type of the input signals. Guided by the theoretical THD expression, the trade-off among the linearity, design complexity, power consumption and chip area can be balanced easily. The presented formula is verified by a design example of 12-bit SAR ADC with dynamic-element-matching (DEM) technique, where the 3-bit LSBs from the SAR ADC are used to generate the randomised DEM state according to the previous THD evaluation. The linearity is enhanced by 9 dB approximately with very low hardware complexity and extremely small extra power consumption of 2 μW.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 2","pages":"189-199"},"PeriodicalIF":1.3,"publicationDate":"2021-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12095","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122497642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Single event transient mitigation techniques for a cross-coupled LC oscillator, including a single-event transient hardened CMOS LC-VCO circuit 交叉耦合LC振荡器的单事件瞬态缓解技术，包括单事件瞬态硬化CMOS LC- vco电路

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-08-28 DOI: 10.1049/cds2.12094

Arumugam Karthigeyan, Sankararajan Radha, Esakkimuthu Manikandan

引用次数: 1

Effect analysis of the teaching method of mutual result correction between students in an experiment of power electronics course 电力电子学实验中学生间互判教学方法的效果分析

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-08-28 DOI: 10.1049/cds2.12096

Guopeng Zhao

{"title":"Effect analysis of the teaching method of mutual result correction between students in an experiment of power electronics course","authors":"Guopeng Zhao","doi":"10.1049/cds2.12096","DOIUrl":"10.1049/cds2.12096","url":null,"abstract":"In order to deepen students' understanding of experimental content and improve the accuracy of experimental results based on improving students' learning initiative, in this study, a teaching method is proposed that lets students check and correct experimental results among themselves after doing experiments. Teachers guide students in experiments but do not check and correct experimental results. At the end of the experiments, students check each other and correct the results of the experiments from the perspective of the teachers. When the experimental results are correct, the experiment ends. If problems are found, the correct experimental results can be obtained by modifying or redoing the experiment. In this study, the sinusoidal pulse width modulation inverter circuit experiment in power electronics course is taken as an example for practical teaching research. There are two classes in this study: one that applies the method and the other that does not. According to the statistics and analysis of the correct rate of experimental results and the answers to thinking questions, students who checked or corrected each other deepened their understanding of the experimental content when both groups did the experiments correctly. When the experimental results of the two groups are different, students can learn from each other, discuss with each other, redo the experiment, and correct wrong results so as to improve the accuracy of the experimental results and the correct answer rate of thinking questions. Through the questionnaire survey, the method proposed in this study enables students to correct the experimental results from the perspective of teachers, thus improving students' awareness of mutual learning and active learning. It can improve the experimental effect.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 3","pages":"201-209"},"PeriodicalIF":1.3,"publicationDate":"2021-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12096","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114452700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Delayered IC image analysis with template-based Tanimoto Convolution and Morphological Decision 基于模板的谷本卷积和形态学决策的延迟IC图像分析

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-08-03 DOI: 10.1049/cds2.12093

Deruo Cheng, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee, Kar-Ann Toh

{"title":"Delayered IC image analysis with template-based Tanimoto Convolution and Morphological Decision","authors":"Deruo Cheng, Yiqiong Shi, Tong Lin, Bah-Hwee Gwee, Kar-Ann Toh","doi":"10.1049/cds2.12093","DOIUrl":"10.1049/cds2.12093","url":null,"abstract":"Supervised machine learning techniques are being pursued for delayered Integrated Circuit (IC) image analysis. However, repetitive data labelling and model training are required for every image set with the supervised techniques. In view of the large scale of IC image set being analysed, techniques that require less human intervention are desired. In this paper, we propose a template-based Tanimoto Convolution and Morphological Decision (TCMD) model for transistor interconnection retrieval in delayered ICs, that is, poly line segmentation, with minimal human intervention. In our proposed TCMD model, prior domain knowledge on the IC images is incorporated into the proposed Tanimoto convolution for generating input feature maps, eliminating the need of filter learning. We further propose morphological decision to process the input feature maps for higher accuracy and robustness on determining poly line positions. With experiments on a delayered IC @90 nm process, our proposed TCMD model achieves 3%∼6% higher accuracy than the reported template-based techniques. Our proposed TCMD model also achieves competitive accuracy with the reported deep U-net while requiring 13× shorter training/validation time. To further improve the pixel-wise precision of the retrieved poly lines, which is important for applications such as analog circuit analysis, we propose a deep learning-based TCMD-PL model. The proposed TCMD-PL model utilises the output of TCMD model as the pseudo labels for training a deep convolutional neural network in supervised manner, and it is able to achieve further performance improvement of ∼4% in comparison to TCMD model without extra data labelling.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 2","pages":"169-177"},"PeriodicalIF":1.3,"publicationDate":"2021-08-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12093","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125680594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Current-voltage model of a graphene nanoribbon p-n junction and Schottky junction diode 石墨烯纳米带pn结和肖特基结二极管的电流-电压模型

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-07-30 DOI: 10.1049/cds2.12092

Samira Shamsir, Laila Parvin Poly, Rajat Chakraborty, Samia Subrina

{"title":"Current-voltage model of a graphene nanoribbon p-n junction and Schottky junction diode","authors":"Samira Shamsir, Laila Parvin Poly, Rajat Chakraborty, Samia Subrina","doi":"10.1049/cds2.12092","DOIUrl":"10.1049/cds2.12092","url":null,"abstract":"This work presents a simplified analytical model of a p-n junction diode based on a graphene nanoribbon (GNR) and a unique type of Schottky diode based on metallic graphene and semi-conducting GNRs. Due to the one-dimensional nature of GNRs, their electrostatic analyses need to be quite different from that of bulk devices. Two approaches have been taken to model the charge distribution in this depletion region, namely, the point charge approximation for the GNR p-n junction diode and the line charge approximation for the graphene/GNR Schottky diode. Analytical expressions for the spatial distribution of electric field and potential have been derived and the results are quite distinct from their bulk counterparts. The current-voltage relation of each diode has been investigated within the approximation of Shockley's law of junctions. The width dependency of the currents for these diodes has also been modelled and it has been found that the current density of both the diodes decreases with decreasing width. Such an analysis can encourage the modelling of next-generation GNR-based high-speed electronic devices.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 2","pages":"157-168"},"PeriodicalIF":1.3,"publicationDate":"2021-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12092","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114647404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

An efficient loop tiling framework for convolutional neural network inference accelerators 卷积神经网络推理加速器的高效循环平铺框架

IF 1.3 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2021-07-20 DOI: 10.1049/cds2.12091

Hongmin Huang, Xianghong Hu, Xueming Li, Xiaoming Xiong

{"title":"An efficient loop tiling framework for convolutional neural network inference accelerators","authors":"Hongmin Huang, Xianghong Hu, Xueming Li, Xiaoming Xiong","doi":"10.1049/cds2.12091","DOIUrl":"10.1049/cds2.12091","url":null,"abstract":"Convolutional neural networks (CNNs) have been widely applied in the field of computer vision due to their inherent advantages in image feature extraction. However, it is difficult to implement CNNs directly on embedded platforms owing to excessive calculations of CNNs. Field Programmable Gate Arrays have been popular in CNN accelerators because of their configurability and high energy efficiency. Given the highly parallel workloads of the CNN, a CNN accelerator with a 14 × 16 processing element array is designed in this study to accelerate the CNN inference. Besides, a loop tiling strategy for convolutional layers is proposed to efficiently transmit feature maps. Additionally, the roofline model is employed to explore the best tiling parameters for optimal performance. Finally, the accelerator written in Verilog-HDL language is implemented on the Xilinx Zynq-7045 evaluation platform. At an operating frequency of 200 MHz, the proposed accelerator can achieve a performance of 57.24 giga operations per second on You Only Look Once v2-tiny and 78.39 GOPS on Visual Geometry Group-16. The accelerator only consumes 224 DSPs, demonstrating a better performance compared with the previous works.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 1","pages":"116-123"},"PeriodicalIF":1.3,"publicationDate":"2021-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12091","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117310869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3