Iet Circuits Devices & Systems最新文献

{"title":"","authors":"","doi":"","DOIUrl":"","url":null,"abstract":"","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148066109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A New High Step-Down Zero Voltage Switching DC–DC Converter With Low Output Current Ripple Suitable for Voltage Regular Module or LED Driver","authors":"Mahmood Vesali","doi":"10.1049/cds2/5049045","DOIUrl":"10.1049/cds2/5049045","url":null,"abstract":"<p>This article proposes a new high step-down converter which, on the input side, there are two series switches. The coupled inductors are used to decrease voltage gain, but on the output side of the proposed converter, two independent inductances are placed and act like interleaved, which cause to decrease output current ripple. Soft switching condition is provided for all semiconductors in the proposed converter. As described, considering the structure of the proposed converter, the converter has two switches, which is the minimum switch used in this structure. Also, the switches do not impose complexity to the converter in terms of control, because these switches are controlled complementary each other. In the structure of the proposed converter, the minimum semiconductor elements are used, which include two switches and three diodes; this design makes the conduction loss of the proposed converter low and achieves higher efficiency. A sample laboratory of the proposed converter is implemented to verify theoretical analysis, which the experimental results are presented in 300 W power with 320 V input voltage and 24 V output voltage. In this test, an efficiency of about 94.6% is achieved.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/5049045","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145686180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Assessment of Data Retainability of 2T DRAM for Processing-In-Memory Application","authors":"Ju Hong Min,&nbsp;Soomin Kim,&nbsp;Jang Hyun Kim,&nbsp;Seongjae Cho","doi":"10.1049/cds2/4669819","DOIUrl":"10.1049/cds2/4669819","url":null,"abstract":"<p>This study examines the influence of cell capacitance on data retention characteristics in dynamic random access memory (DRAM) cells composed of two transistors, in short, 2-transistor (2T) DRAM. The 2T DRAM is gaining attention not only as a standalone memory technology but also as a critical component for processing-in-memory (PIM) applications, offering the full compatibility with standard Si processing. The 2T configuration employs separate transistors for write and read operations, enabling flexible bit-cell design and efficient parallel processing in PIM architectures. However, the small storage node (SN) capacitance, especially when the cell capacitor is truncated, poses challenges for data retention. This work presents a design methodology to enhance data retention in 2T DRAM cells by optimizing transistor dimensions and biasing schemes. Circuit simulations using the 180 nm standard process show that the proposed approach improves retention time by 35% and reduces leakage current by 22% compared to baseline designs. Furthermore, the write transistor current demonstrates a 15% improvement in stability during repeated read operations within the retention time. These results highlight the potential of the proposed design to mitigate retention-related issues and enhance computational accuracy in PIM applications.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/4669819","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145686258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"","authors":"","doi":"","DOIUrl":"","url":null,"abstract":"","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148062314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Multiresponse Image Fusion for High Dynamic Range CMOS Image Sensor Combining Dual Conversion Gain and Logarithmic Response","authors":"Shanshan Lou,&nbsp;Chunyan Li,&nbsp;Qian Jiang,&nbsp;Botao Xiong,&nbsp;Yuchun Chang","doi":"10.1049/cds2/1622944","DOIUrl":"10.1049/cds2/1622944","url":null,"abstract":"<p>This article introduces a multiresponse image fusion method tailored for a high dynamic range (HDR) CMOS image sensor (CIS), which combines dual conversion gain (DCG) and logarithmic responses within a single exposure. Utilizing the imaging characteristics of the sensor together with a proposed quality perceptive strategy, the presented fusion method achieves a light-weight multiresponse fusion stage, which selects the optimal response of the pixels under different illumination from the captured images. The fused image is of better quality compared to a linear combination of weighted images. Moreover, the proposed multiresponse image fusion method can eventually acquire HDR image in real-time.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/1622944","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145619165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"","authors":"","doi":"","DOIUrl":"","url":null,"abstract":"","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148093502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"","authors":"","doi":"","DOIUrl":"","url":null,"abstract":"","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148091062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exploring the Switching Instability of CBRAM for Random Number Generator Applications","authors":"Weixin Xu,&nbsp;Hajira S. Bazaz,&nbsp;Asep Nugroho,&nbsp;Irwan Purnama,&nbsp;Zohreh Hajiabadi,&nbsp;Aiden Graham,&nbsp;Alexander-Hanyu Wang,&nbsp;Sridhar Chandrasekaran,&nbsp;Firman M. Simanjuntak","doi":"10.1049/cds2/9982211","DOIUrl":"10.1049/cds2/9982211","url":null,"abstract":"<p>The coexistence of nonvolatile and volatile switching characteristics in ZnO-based conducting bridge random access memory (CBRAM) devices and the feasibility of the cycle-to-cycle fluctuation of both characteristics for data storage and random number generator (RNG) applications are investigated. The insertion of a 6-nm-thick Ti barrier layer between the Ag top electrode (TE) and the ZnO switching layer improves the switching stability and the memory window up to five orders of magnitude. The employment of current compliance (CC) of 1 mA leads to a permanent LRS; meanwhile, CC lower than 100 uA exhibits volatile switching characteristics. Although the lower CC operations might not be applicable for data storage applications, their switching fluctuations can be used as inputs for generating random bitstreams. An RNG circuit design is proposed, and the randomness of the bitstreams is evaluated using the NIST randomness test suite. The volatile switching induced by the lower CC tends to produce bitstreams with a better randomicity than the nonvolatile one, where the resistance state of the device operated with a CC of 10 uA is able to generate 1600 bits that pass seven out of seven NIST tests. We conduct statistical analysis to shed light on the relationship between the resistance states and the quality of the produced random bitstream. In contrast to popular opinion, the coefficient of variation might not be the best method to quantify the fluctuation of the resistance state in our case. Therefore, we propose the switching fluctuation factor (FF) to determine the threshold value of the resistance state that can produce a sufficient random bitstream; it is found that our RNG circuit requires a threshold FF of 96% to produce a bitstream that passes at least four out of seven tests. This work not only proposes a solution to enhance the switching stability for data storage applications but also provides insight into the exploitation of switching instability for RNG applications, where a single device can be programmed to have both capabilities, rendering programmable and multifunctional electronics.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/9982211","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145619117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"","authors":"","doi":"","DOIUrl":"","url":null,"abstract":"","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148088635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation on High Performance Lead-Free GA0.05FA0.93SnI3-Based Hybrid-Halide Perovskite Solar Cell","authors":"Srinivas Mattaparthi,&nbsp;Didla Sristitha,&nbsp;Banothu Venugopal,&nbsp;Vijay Naik Mudavath,&nbsp;Himanshu Karan","doi":"10.1049/cds2/6765341","DOIUrl":"10.1049/cds2/6765341","url":null,"abstract":"<p>In this article, we present a lead-free hybrid-halide perovskite solar cell (PSC) using guanidinium (GA)-formamidinium tin iodide (GA_0.05FA_0.93SnI₃) as the absorber layer (AL), the performance metrics analyses on the light of short-circuit current (<i>I</i>_sc), power conversion efficiency (PCE), open circuit voltage (<i>V</i>_oc), and fill-factor (FF). Utilizing the SCAPS-1D numerical program, we have optimized the material and device parameters, including thickness of AL, electron affinity, defect density, doping concentration, and series and shunt resistances. The GA_0.05FA_0.93SnI₃ AL exhibits highly stable and nontoxic in nature. The proposed hybrid halide-based PSC achieved an enhanced PCE (27.55%) in comparison with reported cutting-edge PSCs, under the AM1.5G spectrum.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/6765341","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145572175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}