Iet Circuits Devices & Systems最新文献

{"title":"Design of a multi-mode digital pixel with conversion data protection","authors":"Yan-Hua Ma,&nbsp;Xiang-He Kong,&nbsp;Yu-Chun Chang","doi":"10.1049/cds2.12122","DOIUrl":"10.1049/cds2.12122","url":null,"abstract":"<p>With the development of semiconductor technology, digital pixel has received widespread attention and is applied to various electronic products. However, due to the limitation of area, it forms a challenging task to design a digital pixel with multiple modes. In this paper, a pulse width modulation based digital pixel is proposed, which is compatible with five different modes. By using the multi-purpose capacitors and static random access memory structure, it can realise multi-mode conversion in an equivalent area to that of the single mode digital pixel without performance degradation. Furthermore, a corresponding logic control method is developed, such that the integrity of the frame data is ensured during mode conversion. The simulation result of our proposed digital pixel in Tower Jazz 0.18 μm process shows that in the bright field it achieves a dynamic range of 67 dB. In the dark field, it achieves a conversion gain up to 13.91 μV/e−, with input noise of 37.89 e−per pixel after correlated double sampling.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 7","pages":"501-524"},"PeriodicalIF":1.3,"publicationDate":"2022-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12122","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130907035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel design of a silicon PIN diode for increasing the breakdown voltage","authors":"Farzaneh Rezaei,&nbsp;Fatemeh Dehghan Nayeri,&nbsp;Adel Rezaeian","doi":"10.1049/cds2.12120","DOIUrl":"10.1049/cds2.12120","url":null,"abstract":"<p>This paper presents a new structure consisting of a silicon PIN junction with high breakdown voltage and low dark current with two Guard rings. To achieve the optimal structure, the effect of the parameters on the breakdown voltage and the dark current of the device has been investigated and simulated. The intrinsic thickness and impurity, the penetration depth of the active area and guard rings, location and number of guard rings, thickness, and distance between guard rings are the effective parameters of the device's breakdown voltage and dark current. In the proposed structure by placing two guard rings around the active area, the results show that an electric field is distributed at the edge of the active area between the guard rings, which leads to an increase of 292.62 V in breakdown voltage compared to the device without a guard ring.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 6","pages":"491-499"},"PeriodicalIF":1.3,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12120","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124653286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bipartite consensus in coupled harmonic oscillators with local instantaneous interaction and measurement noise","authors":"Zhaoyan Wang,&nbsp;Hengyu Li,&nbsp;Jun Liu,&nbsp;Tiehui Zhang,&nbsp;Xinru Ma,&nbsp;Shaorong Xie,&nbsp;Jun Luo","doi":"10.1049/cds2.12118","DOIUrl":"10.1049/cds2.12118","url":null,"abstract":"<p>This paper investigates the issue of bipartite consensus for coupled harmonic oscillators under the cooperation-competition network topology while considering measurement noise. The concept of bipartite consensus in mean square is established for networked harmonic oscillator systems. In this sense, two consensus algorithms that only use sampled velocity data on the agents in a network are given. Based on the specific structure of the Laplacian matrix related to the cooperation-competition network topology, some sufficient conditions are given to ensure the realisation of the bipartite consensus of the coupled harmonic oscillators. Finally, three examples are provided to illustrate the corresponding theoretical results.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 6","pages":"471-482"},"PeriodicalIF":1.3,"publicationDate":"2022-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12118","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126586157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Calculated characterisation of a sensitive gas sensor based on PEDOT:PSS","authors":"Mokhtar Aarabi,&nbsp;Alireza Salehi,&nbsp;Alireza Kashaninia","doi":"10.1049/cds2.12119","DOIUrl":"10.1049/cds2.12119","url":null,"abstract":"<p>The interactions between poly (3,4-ethylene dioxythiophene) poly (styrenesulfonate) (PEDOT:PSS) and small gas molecules are studied using non-equilibrium Green's function formalism based on the density functional theory. The proposed method is implemented in the Tran SIESTA code to benefit from the potential application of PEDOT:PSS as a gas sensor. The results show that doping with nanoparticles can drastically improve the sensitivity of polymer-based chemical gas sensors. Moreover, among various PEDOT:PSS doping materials, silver nanoparticles have an appropriate response to ammonia, while platinum shows the best response to carbon dioxide. The numerical results can be useful to design PEDOT:PSS-based gas sensors.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 6","pages":"461-470"},"PeriodicalIF":1.3,"publicationDate":"2022-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12119","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122176619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tolerant and low power subtractor with 4:2 compressor and a new TG-PTL-float full adder cell","authors":"Ayoub Sadeghi,&nbsp;Nabiollah Shiri,&nbsp;Mahmood Rafiee,&nbsp;Rahim Ghayour","doi":"10.1049/cds2.12117","DOIUrl":"10.1049/cds2.12117","url":null,"abstract":"<p>A new 1-bit full adder (FA) cell illustrating low-power, high-speed, and a small area is presented by a combination of transmission gate (TG), pass transistor logic (PTL), and float techniques. Using the proposed cell, a 4:2 compressor is implemented and its performance is investigated under diverse circumstances of voltage, temperature, and driving. The process and corners are evaluated through the process-voltage-temperature (PVT) variations and the Monte Carlo method (MCM), respectively. The accuracy and reliability of the proposed 4:2 compressor are confirmed carefully. Utilising the proposed FA and the compressor, an efficient 8-bit subtractor is implemented for bioimage processing, in particular for difference detection of images. A new mechanism is presented to improve the detection performance of digital signal processors (DSPs) by the addition and subtraction of two images for their difference. The quality of the resulted image confirms the efficiency of the proposed circuits and the method. The high performance of the circuits makes them a promising candidate for the next generation of integrated circuits (ICs) applicable to medical image processing.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 6","pages":"437-460"},"PeriodicalIF":1.3,"publicationDate":"2022-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12117","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124149929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A high-performance processor for optimal ate pairing computation over Barreto–Naehrig curves","authors":"Yujun Xie,&nbsp;Bin Wang,&nbsp;Lijun Zhang,&nbsp;Xin Zheng,&nbsp;Xiaoling Lin,&nbsp;Xiaoming Xiong,&nbsp;Yuan Liu","doi":"10.1049/cds2.12116","DOIUrl":"10.1049/cds2.12116","url":null,"abstract":"<p>This paper presents a high-performance processor for optimal ate pairing on Barreto–Naehrig curves over 256-bit prime field at the 128-bit security level. The proposed design exploits parallelism and pipeline at different levels of the pairing algorithm, including the prime field operation, the second extension of the prime field <math>\u0000 <semantics>\u0000 <mrow>\u0000 <mfenced>\u0000 <msub>\u0000 <mi>F</mi>\u0000 <msup>\u0000 <mi>p</mi>\u0000 <mn>2</mn>\u0000 </msup>\u0000 </msub>\u0000 </mfenced>\u0000 </mrow>\u0000 <annotation> $left({F}_{{p}^{2}}right)$</annotation>\u0000 </semantics></math> operation, and operations based on <math>\u0000 <semantics>\u0000 <mrow>\u0000 <msub>\u0000 <mi>F</mi>\u0000 <msup>\u0000 <mi>p</mi>\u0000 <mn>2</mn>\u0000 </msup>\u0000 </msub>\u0000 </mrow>\u0000 <annotation> ${F}_{{p}^{2}}$</annotation>\u0000 </semantics></math>. The proposed design needs 37,271 cycles to compute optimal ate pairings. The results of implementation on a 90 nm standard cell library show that the proposed design consumes 751k gates and can compute the respective pairings in 0.10 ms. This result is at least 60 percent better than related reports in terms of normalised area-time on ASIC. Moreover, the design is also implemented on Xilinx Virtex-6 platform, which consumes 25K Slices and 240 DSPs and takes 0.52 ms to calculate one optimal ate pairing operation.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 5","pages":"427-436"},"PeriodicalIF":1.3,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12116","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128482462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"1.2 kV 4H-SiC planar power MOSFETs with a low-K dielectric in central gate","authors":"Dong Liu,&nbsp;Mingyue Li,&nbsp;Yangjie Ou,&nbsp;Zhong Lan,&nbsp;Maosen Tang,&nbsp;Weibo Wang,&nbsp;Xiarong Hu","doi":"10.1049/cds2.12115","DOIUrl":"10.1049/cds2.12115","url":null,"abstract":"<p>A 1.2 kV 4H-SiC planar power MOSFET with a low-K dielectric in central gate (LK-MOS) is proposed in this paper. The LK-MOS features a P+ shielding region and a thick low-K dielectric layer under the central gate. The insulation layer capacitance is reduced by the thick low-K dielectric, while the depletion layer capacitance is decreased due to the reduced gate-to-drain overlap. The LK-MOS is demonstrated to have 97.8%, 70.6%, and 52.2% lower HF-FOM (<i>R</i>_on × <i>C</i>_gd), and 98.9%, 97.4%, and 69.4% lower HF-FOM (<i>R</i>_on × <i>Q</i>_gd), when compared with that of the conventional MOSFET (C-MOS), Buffered-Gate MOSFET (BG-MOS) and Thick Central Oxide MOSFET (TCOX-MOS), respectively. Besides, the LK-MOS can also have 16.8%, 5.9% lower <i>C</i>_gs, and 19.9%, 12.4% lower <i>Q</i>_gs compared with that of BG-MOS and TCOX-MOS.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 5","pages":"419-426"},"PeriodicalIF":1.3,"publicationDate":"2022-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12115","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123120657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Onto a higher power handling for very high frequency direct antenna modulation","authors":"Jean Paul D. Santos,&nbsp;Kamal Bhakta,&nbsp;Foad Fereidoony,&nbsp;Yuanxun Ethan Wang","doi":"10.1049/cds2.12108","DOIUrl":"10.1049/cds2.12108","url":null,"abstract":"<p>Antennas constrained to platforms that require miniaturisation, significantly smaller than the wavelength of the desired frequency, are inefficient radiators and limited to narrowband operations. To overcome these limitations, a technique called direct antenna modulation (DAM), is incorporated with electrically small antennas to enable transmission of high-bandwidth signals through narrowband antennas. DAM utilises switching circuitry to directly modulate the antenna at its corresponding peak energy moments all while being synchronised to the input signal, yet previous iterations were susceptible to low transmit powers due to limitations in the switching network's power handling capability and tremendous coupling between transistor ports that results in an ambiguous switching signal at the gate. A frequency shift keyed (FSK) DAM antenna topology is proposed, which is capable of high-power transmission through a geometrically symmetrical switching circuitry integrating pairs of complementary GaN transistors. The symmetry assists in removing coupling among transistor ports to effectively switch the transistors OFF and ON without regard to the input RF power. The authors’ theoretical analysis agrees with our simulations and far-field measurements which show the FSK DAM antenna topology is capable of transmit powers up to −1 dBm given a 42 dBm of input RF power.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 5","pages":"373-381"},"PeriodicalIF":1.3,"publicationDate":"2022-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12108","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124843088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An energy-efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications","authors":"Hamid Mahmoodian,&nbsp;Mehdi Dolatshahi,&nbsp;S. Mohammadali Zanjani,&nbsp;Mohammad Amin Honarvar","doi":"10.1049/cds2.12112","DOIUrl":"10.1049/cds2.12112","url":null,"abstract":"<p>In this paper, a latch-based energy-efficient dynamic comparator is presented in Carbon Nanotube Field Effect Transistor (CNTFET) technology. The proposed comparator consists of two main stages: pre-amplifier and latch. The latch stage is designed for the main purpose of low-power consumption and high-speed performances. The proposed speed-up technique for the latch structure controls the threshold voltage (<i>V</i>_th) of the cross-coupled inverters. So, the delay of the latch stage decreases and consequently, the overall delay of the comparator circuit is also reduced up to 19.4% while the maximum speed performance of the proposed comparator increases by 54% compared to the conventional double-tail dynamic comparator. Additionally, the use of the proposed distinctive structure for the tail transistors in the latch stage, leads to more than 11% reduction in the energy per conversion of the proposed circuit compared to the conventional double-tail dynamic comparator. To verify the circuit performances, the comparator circuit is simulated in HSPICE using 32 nm CNTFET Stanford model technology parameters. The simulation results show that the proposed comparator with the proposed speed-up approach can operate up to 14.2 GHz with a sensitivity of 30 μV at the supply voltage of 1 V, while consumes only 42.38 μW of power. Therefore, the proposed comparator can be used in high-resolution (up to 12 bit) and high-speed low-power analogue-to-digital converter applications. Moreover, the effects of the non-ideal fabrication process (including the pitch and the threshold voltage variations), supply voltage and temperature variations are investigated in this work. Monte-Carlo analysis shows that the standard deviation of the offset voltage is approximately 1.24 mV. Finally, the kickback noise of the proposed comparator is obtained as 80 μV, which shows the proper performance of the proposed comparator circuit in comparison with other reported designs.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 4","pages":"360-371"},"PeriodicalIF":1.3,"publicationDate":"2022-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12112","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114850258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optical properties of a-Si:H thin-film transistors by illumination by white light with different colour temperatures","authors":"Jui-Hung Chang,&nbsp;Chia-Lun Lee,&nbsp;Fu-Hsing Chen,&nbsp;Chih-Lung Lin","doi":"10.1049/cds2.12114","DOIUrl":"10.1049/cds2.12114","url":null,"abstract":"<p>This work investigates the optical properties of hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) using the transmittances of colour filters and the spectra of commercialised white light-emitting diodes (LEDs). The ratios of the measured photocurrents obtained using the TFTs that are covered and are not covered colour filters are related to the effective illumination from white LEDs with different colour temperatures that pass through the colour filters. A new factor that is based on these ratios of photocurrents is proposed to evaluate the output characteristics of optical sensors with our previously developed white-light photocurrent gating (WPCG) structure. The analytical results demonstrate that the proposed factor and the output voltages of the WPCG structure are highly correlated with each other, favouring the optimisation of the design parameters to realise an optical sensor that is highly reliable under diverse conditions for use in large interactive displays.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"16 5","pages":"399-409"},"PeriodicalIF":1.3,"publicationDate":"2022-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12114","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124302734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}