Iet Circuits Devices & Systems最新文献_第7页

WITHDRAWAL: Digital Twin Structure Monitoring System and Key Technologies of Distribution Network Based on Intelligent Communication Network 摘要：基于智能通信网的配电网数字双结构监控系统及关键技术

IF 1.8 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-12-12 Epub Date: 2026-05-11 DOI: 10.1049/cds2.12148

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WITHDRAWAL: Digital Twin Structure Monitoring System and Key Technologies of Distribution Network Based on Intelligent Communication Network 摘要：基于智能通信网的配电网数字双结构监控系统及关键技术

IF 1.8 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-12-12 Epub Date: 2026-05-11 DOI: 10.1049/cds2.12148

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WITHDRAWAL: Memristor based 8 T SRAM Cell with New Reliability Concern on noise voltage parameter for Neuromorphic Memory for Smart Industries 基于记忆电阻器的8 T SRAM单元及其对智能工业神经形态存储器噪声电压参数可靠性的新关注

IF 1.8 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-12-12 Epub Date: 2026-07-19 DOI: 10.1049/cds2.12146

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WITHDRAWAL: Memristor based 8 T SRAM Cell with New Reliability Concern on noise voltage parameter for Neuromorphic Memory for Smart Industries 基于记忆电阻器的8 T SRAM单元及其对智能工业神经形态存储器噪声电压参数可靠性的新关注

IF 1.8 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-12-12 Epub Date: 2026-07-19 DOI: 10.1049/cds2.12146

引用次数: 0

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-12-11

引用次数: 0

Accuracy Improvement in Approximate Sum of Absolute Differences Circuit Using Error Correction Module for Difference Detection in Bio-Images 误差校正模块用于生物图像差分检测的近似绝对差分和电路精度的提高

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-12-11 DOI: 10.1049/cds2/5943150

Forouzan Bahrami, Saina Parvanehnezhad Shirazian, Nabiollah Shiri

{"title":"Accuracy Improvement in Approximate Sum of Absolute Differences Circuit Using Error Correction Module for Difference Detection in Bio-Images","authors":"Forouzan Bahrami, Saina Parvanehnezhad Shirazian, Nabiollah Shiri","doi":"10.1049/cds2/5943150","DOIUrl":"10.1049/cds2/5943150","url":null,"abstract":"Approximate computing (AC)-based arithmetic circuits have not been reliable in sensitive applications like difference detection of bioimages. This article declares that the challenge is not established constantly. Accordingly, a new AC-based compressor with 16 transistors based on compound gates is proposed. The cell is implemented by complementary metal–oxide-semiconductor (CMOS) technology, and a novel approximate sum of absolute differences (SADs) unit is proposed using the compressor. Also, an error-correction module (ECM) is presented to improve the accuracy and error reduction of approximate SAD. The circuit performance and the accuracy of the output image after embedding the compressor in SAD are extracted, and the results show the superiority of the proposed circuits. The acceptable accuracy and performance of the SAD are proven versus standard and bioimages. In comparison with the exact type, the represented approximate 4:2 compressor reduces the power and power-delay-product (PDP) by 80% and 96%, respectively, while the utilization of the proposed compressor in SAD decreases the average power by 35% and reduces 43% of the average PDP. The quality and accuracy of the figure of merits (FoMs) support the main idea of this study for a new generation of AC-based circuits that are applicable in bioimage processing.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/5943150","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145750794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-12-10

引用次数: 0

A Time-Interleaved Swept-Threshold ADC With Stable Timing for IR-UWB Medical Radars 用于IR-UWB医用雷达的时序稳定的时间交错扫描阈值ADC

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-12-10 DOI: 10.1049/cds2/2086966

Parisa Amiri, Javad Yavandhasani

{"title":"A Time-Interleaved Swept-Threshold ADC With Stable Timing for IR-UWB Medical Radars","authors":"Parisa Amiri, Javad Yavandhasani","doi":"10.1049/cds2/2086966","DOIUrl":"10.1049/cds2/2086966","url":null,"abstract":"This paper presents a new method for direct sampling of the backscattered signal in ultrawideband (UWB) impulse radar for vital sign detection. One of the standard methods for direct sampling in UWB radars is the time-interleaving technique. In these converters, NOT gates (logical inverter gates) and tunable delay cells are typically used to create time delays and generate delayed replicas of the sampling clock. However, the challenge arises from the nonuniform delay associated with these gates and dependency on the process, voltage, and temperature (PVT), which affects the converter spurious-free dynamic range (SFDR). This paper employs a new structure using a ring counter to overcome this issue. As a result, a stable and PVT-independent sampling clock is obtained without significant overhead, compared to the conventional inverter-based delay cells approach. The proposed flip-flop-based ring counter architecture eliminates the need for analog delay tuning, offering a fully digital, PVT-resilient solution for uniform sampling in high-speed radar systems. The proposed structure has been utilized to design a 12-channel, six-bit time-interleaved swept-threshold analog to digital converter (ADC). The ADC has been in 65 nm complementary metal-oxide-semiconductor (CMOS) technology and simulated using the foundry design kit. Postlayout simulation results demonstrate a total power consumption of 28.54 mW with a 16.66 GS/s sampling rate.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/2086966","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145739682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-12-09

引用次数: 0

Energy-Efficient and Area-Optimized Reversible Carry Select Adder 节能和面积优化可逆进位选择加法器

IF 1.2 4区工程技术

Iet Circuits Devices & Systems Pub Date : 2025-12-09 DOI: 10.1049/cds2/4179235

Praveena Murugesan, Palani S., Divya V.

{"title":"Energy-Efficient and Area-Optimized Reversible Carry Select Adder","authors":"Praveena Murugesan, Palani S., Divya V.","doi":"10.1049/cds2/4179235","DOIUrl":"10.1049/cds2/4179235","url":null,"abstract":"The carry select adder (CSA) is a highly efficient arithmetic component commonly utilized in digital systems due to its superior speed performance. In the context of energy-efficient computing and fault-tolerant quantum computing, reversible logic emerges as a critical technology owing to its potential to reduce energy dissipation by retaining information. This article introduces an efficient design for a reversible carry select adder (ERCSA), constructed using fundamental lossless logic gates such as modified TSG (MTSG), Peres, and Fredkin Gate (FRG). The proposed design eliminates the need to compute the carry for the default carry input of “1.” Additionally, an optimized architecture is proposed to reduce the quantum cost of the circuit. The design achieves significant improvements by minimizing quantum cost, unused outputs, and gate count, while ensuring scalability for higher bit-width additions. A comparative analysis with existing reversible adder highlights substantial performance enhancements, including reduction in the number of gates (35.4%), garbage outputs (18.9%), ancillary inputs (25%), quantum cost (22.7%), and delay (29.5%) compared to recent designs. The proposed architecture was modeled in Verilog and synthesized using Xilinx Vivado Design Suite targeting the Xilinx Artix-7 FPGA family. The proposed 16-bit ERCA architecture achieves 10.86% lower power, 76.43% reduced delay, and 21.7% better area efficiency compared to existing methods. These improvements make it highly suitable for low-power and high-speed VLSI applications.","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":"2025 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2025-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cds2/4179235","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145739597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0