Design and optimisation of high-efficient class-F ULP-PA using envelope tracking supply bias control for long-range low power wireless local area network IEEE 802.11ah standard using 65 nm CMOS technology

Abstract

This article presents the design and optimisation of a sub-1 GHz class-F ultra-low power (ULP) power amplifier (PA) in 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. An envelope tracking (ET) supply biasing technique is adopted to improve the efficiency of class-F PA. The ET consist of a pre-amp right before the detector in order to enhance the efficiency and save adequate amount of dc power consumption. The PA consists of two cascode cells terminated as class-F with gate-to-drain feedback in order to enhance linearity and limit any harmonic component from the input signal. The novel design consumes a dc power of 3.75 mW, power added efficiency of 37.1%, operating at 915–925 MHz unlicensed band and total saturated output power of 22 dBm including 14 dBm power gain at PA, which qualifies under long-range low power wireless local area network IEEE 802.11ah standard. The inductor-less design for ET supply bias reduces the chip layout size to 0.13 mm² only.