1 - 5ghz 22mw接收器前端,主动反馈基带和电压换流混频器,65nm CMOS

IF 1 4区 工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC
Benqing Guo, Haishi Wang, Huifen Wang, Lei Li, Wanting Zhou, Kianoosh Jalali
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引用次数: 6

摘要

提出了一种带无源电压换流混频器的CMOS基带有源反馈接收机前端。有源反馈基带通过同时构建RF带通滤波器和BB低通滤波器实现带内信号放大和带外阻断器干扰抑制。嵌入电流镜的电压整流混频器显著降低了本LO发生器的功率要求。为了进一步提高功率效率,通常采用堆叠n/pMOS结构。接收器前端采用标准65nm CMOS工艺设计。仿真结果表明,在1 ~ 5 GHz本端频率范围内,该滤波器的NF值为3.4 dB,最大增益为32 dB。得到的带内IIP3为−12dbm,带外IIP3为9dbm。接收机前端核心在1ghz本端频率下的功耗仅为22mw,占地面积为645 × 543 μm2,适合手持终端的低功耗应用。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

A 1–5 GHz 22 mW receiver frontend with active-feedback baseband and voltage-commutating mixers in 65 nm CMOS

A 1–5 GHz 22 mW receiver frontend with active-feedback baseband and voltage-commutating mixers in 65 nm CMOS

A CMOS baseband-active-feedback receiver frontend with passive voltage-commutating mixers is proposed. The active feedback baseband enables in-band signal amplification and out-of-band blocker interference suppression by constructing the RF bandpass filter and BB lowpass filter, simultaneously. The voltage-commutating mixers embedded in current mirrors significantly reduce the power requirement for the LO generator. The stacked n/pMOS structure is commonly adopted to further improve power efficiency. The receiver frontend is designed in a standard 65 nm CMOS process. Simulation results display an NF of 3.4 dB and a maximum gain of 32 dB from 1 to 5 GHz LO frequency range. The obtained in-band and out-of-band IIP3 are −12 dBm and 9 dBm, respectively. The receiver frontend core only consumes 22 mW at 1 GHz LO frequency and occupies the area of 645 × 543 μm2, which is suitable for the low-power application of handheld terminals.

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来源期刊
Iet Circuits Devices & Systems
Iet Circuits Devices & Systems 工程技术-工程:电子与电气
CiteScore
3.80
自引率
7.70%
发文量
32
审稿时长
3 months
期刊介绍: IET Circuits, Devices & Systems covers the following topics: Circuit theory and design, circuit analysis and simulation, computer aided design Filters (analogue and switched capacitor) Circuit implementations, cells and architectures for integration including VLSI Testability, fault tolerant design, minimisation of circuits and CAD for VLSI Novel or improved electronic devices for both traditional and emerging technologies including nanoelectronics and MEMs Device and process characterisation, device parameter extraction schemes Mathematics of circuits and systems theory Test and measurement techniques involving electronic circuits, circuits for industrial applications, sensors and transducers
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