Challenges and solutions of working under threshold supply-voltage, for CNTFET-based SRAM-bitcell

Recently, several studies were done on SRAM bitcells at different supply-voltages; upper, near or lower to threshold voltage. To the best of the author's knowledge, none of them discussed at threshold supply-voltage with proper subthreshold operations and Nano/Pico power-dissipations, hence this paper decides to investigate challenges and solutions of designing at $V_{DD}$ =  $V_{th}$, because this voltage will lead to having lower power consumptions. This research applies power-gating technique to adjust $V_{DD}$ on $V_{th}$, and also utilises output-inverter to set Logic 1 at $V_{DD}$. Although ‘power-gating’ and ‘output-inverter’ were used in other works, this study renders specific points about them. In fact, the ability of power-gating technique in adjusting $V_{DD}$ on $V_{th}$ without any instabilities in bitcell operation was not reported before, as well as, the idea of employing output-inverter in read path for setting Logic-1 at $V_{DD}$. It also proposed SNM% as a useful figure-of-merit. The goal of this study is not to present new circuits for bitcell, but is to investigate challenges and solutions of working under ‘$V_{DD}=V_{th}$’ which these solutions can lead to having an optimum bitcell.