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1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

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A 40K cache memory and memory management unit 40K高速缓存和内存管理单元
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156968
J. Cho, J. Kaku
{"title":"A 40K cache memory and memory management unit","authors":"J. Cho, J. Kaku","doi":"10.1109/ISSCC.1986.1156968","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156968","url":null,"abstract":"The development of a cache memory to support 32b microprocessors will be offered. Including an on-chip memory unit the circuit operates at 33MHz, delivers data to the CPU in 2/4 clock cycles and is fabricated in 2μm CMOS.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126271214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 4b × 4b multiplier and 3b counter in Josephson threshold logic 约瑟夫森阈值逻辑中的4b × 4b乘法器和3b计数器
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156938
Y. Hatano, Y. Harada, K. Yamashita, U. Kawabe
{"title":"A 4b × 4b multiplier and 3b counter in Josephson threshold logic","authors":"Y. Hatano, Y. Harada, K. Yamashita, U. Kawabe","doi":"10.1109/ISSCC.1986.1156938","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156938","url":null,"abstract":"This Paper will report on the development of a 4×4b parallel multiplier with a carry-to-carry delay time of 279ps and a 3b binary counter operating at 2.2 GHz implemented in Josephson junction technology.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"466 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125828645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Practical limits of IC testers IC测试仪的实际限制
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156932
J. Trnka
{"title":"Practical limits of IC testers","authors":"J. Trnka","doi":"10.1109/ISSCC.1986.1156932","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156932","url":null,"abstract":"As analog and digital integrated circuits achieve higher levels of integration, testing and test time become a more serious production problem. To keep testing under control, manufacturers are relying on several methods to obtain an acceptable quality level for ICs. These include tighter process control, high temperature testing, limited pattern tests, special circuits for test, and wafer rejection criteria. The panel will provide integrated circuit producer's viewpoints on testing to meet quality level targets, and user's perspective on how well they are doing.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121902087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 50Mb/s CMOS optical data link receiver integrated circuit 50Mb/s CMOS光数据链路接收集成电路
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156874
J. Steininger, E. Swanson
{"title":"A 50Mb/s CMOS optical data link receiver integrated circuit","authors":"J. Steininger, E. Swanson","doi":"10.1109/ISSCC.1986.1156874","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156874","url":null,"abstract":"This report will cover an optical data link circuit designed in a 1.5μm CMOS technology. Operation is from 1Mb/s to 50Mb/s with a 60dB dynamic range: input currents are as low as 100nA rms. The chip requires a single 5V power supply and internally generates a bias voltage for the PIN diode.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129114517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Hybrid silicon wafer-scale packaging technology 混合硅晶圆级封装技术
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156981
R. Johnson, J. Davidson, R. Jaeger, D. Kerns
{"title":"Hybrid silicon wafer-scale packaging technology","authors":"R. Johnson, J. Davidson, R. Jaeger, D. Kerns","doi":"10.1109/ISSCC.1986.1156981","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156981","url":null,"abstract":"Procedures developed for mounting ICs in holes in a silicon wafer and inter-connecting them, via two-level metalization, will be presented. The performance of the interconnections at high speeds will be compared with traditional hybrid assemblies.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133072918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 1Mb CMOS DRAM with design-for-test functions 具有专为测试而设计功能的1Mb CMOS DRAM
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156947
J. Neal, B. Holland, S. Inoue, W. Loh, H. McAdams, Kenneth A. Poteet
{"title":"A 1Mb CMOS DRAM with design-for-test functions","authors":"J. Neal, B. Holland, S. Inoue, W. Loh, H. McAdams, Kenneth A. Poteet","doi":"10.1109/ISSCC.1986.1156947","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156947","url":null,"abstract":"A mask programmable 1Mb CMOS DRAM family has been developed featuring design-for-test functions which allow the memory to reconfigured as an 8b parallel 128Kb organization to reduce test time. With a 1μm twin-well CMOS technology and a contactless trench cell, the chip measures 49mm2.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134033088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A micro-programmable realtime image processor 微可编程实时图像处理器
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1157003
T. Mori, K. Aono, H. Sakai, K. Hasegawa, H. Yamada, T. Takemoto
{"title":"A micro-programmable realtime image processor","authors":"T. Mori, K. Aono, H. Sakai, K. Hasegawa, H. Yamada, T. Takemoto","doi":"10.1109/ISSCC.1986.1157003","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1157003","url":null,"abstract":"A micro-programmable realtime image processor with an instruction cycle of 20ns will be described. A 7×7mm2, 45K transistor chip has been designed in a self-aligned bipolar technology. Dissipation is 2.5W.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"10 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114020702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 50fA input current junction-isolated JFET opamp 50fA输入电流结隔离型JFET运放
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156959
J. Close, L. Counts
{"title":"A 50fA input current junction-isolated JFET opamp","authors":"J. Close, L. Counts","doi":"10.1109/ISSCC.1986.1156959","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156959","url":null,"abstract":"A monolithic opamp with measured 50fA input currents, 0.25mV offset and 5μV/°C offset drift will be reported. The amplifier uses a JFET developed for standard junction-isolated processing that can offer a 10× reduction in input current over other bipolar-compatible JFETs.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115608221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Digital processors for a video decoder using oversampling 一种使用过采样的视频解码器数字处理器
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1157004
L. Paris, P. Senn
{"title":"Digital processors for a video decoder using oversampling","authors":"L. Paris, P. Senn","doi":"10.1109/ISSCC.1986.1157004","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1157004","url":null,"abstract":"A report on two-chip implementation of a composite-to-RGB decoder utilizing oversampling filters and color lookup tables will be offered. The processor attains a 27MHz speed in a 3μm NMOS implementation with 900mW dissipation.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128817778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A CMOS 1Mb EPROM 一个CMOS 1Mb EPROM
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156906
B. Venkatesh, M. Ahrens, Wei Liu, H. Partovi, D. Rinerson, Jih Lien, Tong Wang, S. Govindachar, D. Rogers
{"title":"A CMOS 1Mb EPROM","authors":"B. Venkatesh, M. Ahrens, Wei Liu, H. Partovi, D. Rinerson, Jih Lien, Tong Wang, S. Govindachar, D. Rogers","doi":"10.1109/ISSCC.1986.1156906","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156906","url":null,"abstract":"A 1Mb CMOS EPROM with 150ns access time power dissipation of 250mW and cell size of 20.25μm<sup>2</sup>will be described. The die measures 79K mil<sup>2</sup>.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125303643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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