40K高速缓存和内存管理单元

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1986.1156968

J. Cho, J. Kaku

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引用次数: 5

摘要

将提供支持32b微处理器的高速缓存存储器的开发。该电路包括一个片上存储单元，工作频率为33MHz，以2/4个时钟周期向CPU提供数据，采用2μm CMOS制造。

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A 40K cache memory and memory management unit

The development of a cache memory to support 32b microprocessors will be offered. Including an on-chip memory unit the circuit operates at 33MHz, delivers data to the CPU in 2/4 clock cycles and is fabricated in 2μm CMOS.

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来源期刊

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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