1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

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A digital processor for decoding of composite TV signals using adaptive filtering 一种使用自适应滤波对复合电视信号进行解码的数字处理器
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1986-10-01 DOI: 10.1109/ISSCC.1986.1157019
M. Yoshimoto, S. Nakagawa, K. Murakami, S. Asai, Y. Akasaka, Y. Nakajima, Y. Horiba
{"title":"A digital processor for decoding of composite TV signals using adaptive filtering","authors":"M. Yoshimoto, S. Nakagawa, K. Murakami, S. Asai, Y. Akasaka, Y. Nakajima, Y. Horiba","doi":"10.1109/ISSCC.1986.1157019","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1157019","url":null,"abstract":"The adaptive separation of color TV signals into luminance/ chrominance components and color compensation using an 8b pipelined signal processor with a 2-line store will be described. A 2μm CMOS IC was designed for implementation with an 18K serial memory operated at 17.7MHz. Dissipation is 450mW.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1986-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125129437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Technology commentary - In perspective: The tunnel diode 技术评论-透视:隧道二极管
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156891
R. Swartz
{"title":"Technology commentary - In perspective: The tunnel diode","authors":"R. Swartz","doi":"10.1109/ISSCC.1986.1156891","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156891","url":null,"abstract":"In the late 50s and early 60's, speed was an important concern in electronics. Then, bipolar was the dominant transistor technology, although MOS was on the way and CMOS was soon to be proposed. Even though little yet existed in the way of integrated circuit technology, the foundations were already laid for most of the popular bipolar IC logic configurations of today. Propagation delays for RTL and diode-resistor-transistor type logic were on the order of 50ns, although certain novel configurations based on high performance bipolar discretes had operating speeds 10 times faster. Solid-state microwave circuits were based largely on varactor diode parametric amplifiers and negative resistance oscillators with operating frequencies in the range of 1-1OGHz.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115307355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 11GHz hybrid paraphase amplifier 一个11GHz混合错码放大器
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156894
Yiwei Chen, J. Beyer, V. Sokolov, J. Culp
{"title":"A 11GHz hybrid paraphase amplifier","authors":"Yiwei Chen, J. Beyer, V. Sokolov, J. Culp","doi":"10.1109/ISSCC.1986.1156894","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156894","url":null,"abstract":"This report will cover a microwave hybrid distributed amplifier for conversion of single-ended inputs to balanced outputs. Included is anm-derived drain line with a useful bandwidth over 14.5GHz and a phase deviation of less than±50°and amplitude variations less than 1dB.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115335128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A voiceband 15b interpolative converter chip set 一种话音波段15b插值转换器芯片组
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156917
K. Yamakido, S. Nishita, M. Kokubo, H. Shirasu, K. Ohwada, T. Nishihara
{"title":"A voiceband 15b interpolative converter chip set","authors":"K. Yamakido, S. Nishita, M. Kokubo, H. Shirasu, K. Ohwada, T. Nishihara","doi":"10.1109/ISSCC.1986.1156917","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156917","url":null,"abstract":"Linear A/D and D/A converters using a multilevel quantizing interpolation technique will be described. The devices empoly 2μm CMOS 5V single supply chips providing 15b resolution with sampling rates as high as 512kHz.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125046164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Liquid nitrogen cooled CMOS 液氮冷却CMOS
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156921
F. Gaensslen
{"title":"Liquid nitrogen cooled CMOS","authors":"F. Gaensslen","doi":"10.1109/ISSCC.1986.1156921","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156921","url":null,"abstract":"Mainframe computers are still the exclusive domain of bipolar technology. In the near future, however, it is believed a large-scale liquid-nitrogen cooled CMOS computer system may Become available. Liquid nitrogen temperature (77°K) operation economically combines bipolar speeds with MOS circuit densities and power levels. Changing the ambient temperature raises additional issues including packaging, testing and reliability.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125245593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 120kHz sigma/delta A/D converter 120kHz σ / δ A/D转换器
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156997
R. Koch, B. Heise
{"title":"A 120kHz sigma/delta A/D converter","authors":"R. Koch, B. Heise","doi":"10.1109/ISSCC.1986.1156997","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156997","url":null,"abstract":"This paper will cover a sigma/delta A/D converter employing two integrators. The converter achieves lib linearity and resolution with 15MHz clock for a 120kHz baseband Signal. A single 5V supply and 15MHz amplifiers are used. The intended application is for an ISDN echo canceler.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125533659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Modeling power-supply disturbances in digital circuit 数字电路中电源干扰的建模
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1157008
M. Cortes, E. McCluskey, K. Wagner, Dawei Lu
{"title":"Modeling power-supply disturbances in digital circuit","authors":"M. Cortes, E. McCluskey, K. Wagner, Dawei Lu","doi":"10.1109/ISSCC.1986.1157008","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1157008","url":null,"abstract":"A model that represents errors caused by power supply disturbances as delay faults will be discussed. Experiments reveal that the error susceptibility increases at high clock rates and that metastable states may result.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114942931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 20MHz 32b pipelined CMOS image processor 一个20MHz 32b流水线CMOS图像处理器
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156909
A. Kanuma, M. Noda, H. Nihira, T. Yaguchi, N. Ikumi, C. Hori, M. Sugai, K. Suzuki
{"title":"A 20MHz 32b pipelined CMOS image processor","authors":"A. Kanuma, M. Noda, H. Nihira, T. Yaguchi, N. Ikumi, C. Hori, M. Sugai, K. Suzuki","doi":"10.1109/ISSCC.1986.1156909","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156909","url":null,"abstract":"A 32b image processor with writable control stores that can process a 1024-point complex FFT in 1ms, has been developed. This paper will report on features which include fabrication in 1.2μm N-well CMOS, use of double layer metal technology and the integration of 170K transistors. Dissipation is 750mw at 5V.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114274872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Microprocessors in the year 2001 2001年的微处理器
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156935
J. Slager
{"title":"Microprocessors in the year 2001","authors":"J. Slager","doi":"10.1109/ISSCC.1986.1156935","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156935","url":null,"abstract":"When the first microprocessor was introduced in '71, few could have imagined the phenomenal growth of the industry over the next fifteen years. Future growth is now threatened due to physical limitations and the inability to utilize fully the potential of computers, because of bottlenecks at the man-machine interface. Panelists will appraise these conditions and the steps to take to prepare for a similar period of spectactular advances.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128464058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 4Mb DRAM with half internal-voltage bitline precharge 内置半电压位线预充电的4Mb DRAM
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1157014
M. Takada, T. Takeshima, M. Sakamoto, T. Shimizu, H. Abiko, T. Katoh, M. Kikuchi, S. Takahashi, Y. Sato, Y. Inoue
{"title":"A 4Mb DRAM with half internal-voltage bitline precharge","authors":"M. Takada, T. Takeshima, M. Sakamoto, T. Shimizu, H. Abiko, T. Katoh, M. Kikuchi, S. Takahashi, Y. Sato, Y. Inoue","doi":"10.1109/ISSCC.1986.1157014","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1157014","url":null,"abstract":"micrograph of BSE cells with folded A1 bitline structure. The cell has high immunity against alpha-particle soft errors, because the buried polysilicon electrode stores the signal charge, while a heavily doped substrate of a P/P+t epitaxial wafer serves as the counter-electrode. The cell size is 2.3 x 4.6p with a 50fF storage capacitance and 51.1 trench depth. In 4Mb DRAM design the bitline driving high voltage must be limited to prevent the characteristic degradation of 1p gate cell transistors, and to suppress the voltage bounce of the cell capacitor electrode substrate due to BSE cells. Figure 2 shows the internal voltage converter circuitry that served to solve the problem. The bitline driving source voltage VBLS is set first by the limiter voltage VL and then by the word line driving source voltage VWLS. Since a depletion type transistor QT is used in VL to VWLS conversion, VL can be preset at a relatively low voltage (about 3V), which affords constant voltage generation in a wider Vcc range than in a conventional limiter circuit?. Figure 3 shows the characteristics for converted internal voltages VL, VWLS, VBLS and bitline precharge voltage VBLP. At Vcc above 4V, VBLP remains at a constant voltage, between 1.6 to 1.8V, approximately-, while at Vcc below 4V, VBLS becomes nearly equal to Vcc, which means conventional VCc/2 precharge is realized. Figure 4 shows the 4Mb memory array organization, sense bitline circuitry and sense timing diagram. The memory array was divided into 16 256Kb-blocks, half of which are selectively activated in each access cycle, leaving the other blocks in a standby mode to reduce power consumption and suppress the substrate voltage bounce. In a memory The key technologies required to develop the DRAM were: Buried","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XXIX 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128736758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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