数字电路中电源干扰的建模

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1986.1157008

M. Cortes, E. McCluskey, K. Wagner, Dawei Lu

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引用次数: 7

摘要

将讨论一个将电源干扰引起的误差表示为延迟故障的模型。实验表明，在高时钟速率下，误差敏感性增加，并可能产生亚稳态。

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Modeling power-supply disturbances in digital circuit

A model that represents errors caused by power supply disturbances as delay faults will be discussed. Experiments reveal that the error susceptibility increases at high clock rates and that metastable states may result.

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1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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