A 4Mb DRAM with half internal-voltage bitline precharge

Abstract

micrograph of BSE cells with folded A1 bitline structure. The cell has high immunity against alpha-particle soft errors, because the buried polysilicon electrode stores the signal charge, while a heavily doped substrate of a P/P+t epitaxial wafer serves as the counter-electrode. The cell size is 2.3 x 4.6p with a 50fF storage capacitance and 51.1 trench depth. In 4Mb DRAM design the bitline driving high voltage must be limited to prevent the characteristic degradation of 1p gate cell transistors, and to suppress the voltage bounce of the cell capacitor electrode substrate due to BSE cells. Figure 2 shows the internal voltage converter circuitry that served to solve the problem. The bitline driving source voltage VBLS is set first by the limiter voltage VL and then by the word line driving source voltage VWLS. Since a depletion type transistor QT is used in VL to VWLS conversion, VL can be preset at a relatively low voltage (about 3V), which affords constant voltage generation in a wider Vcc range than in a conventional limiter circuit?. Figure 3 shows the characteristics for converted internal voltages VL, VWLS, VBLS and bitline precharge voltage VBLP. At Vcc above 4V, VBLP remains at a constant voltage, between 1.6 to 1.8V, approximately-, while at Vcc below 4V, VBLS becomes nearly equal to Vcc, which means conventional VCc/2 precharge is realized. Figure 4 shows the 4Mb memory array organization, sense bitline circuitry and sense timing diagram. The memory array was divided into 16 256Kb-blocks, half of which are selectively activated in each access cycle, leaving the other blocks in a standby mode to reduce power consumption and suppress the substrate voltage bounce. In a memory The key technologies required to develop the DRAM were: Buried