A. Kanuma, M. Noda, H. Nihira, T. Yaguchi, N. Ikumi, C. Hori, M. Sugai, K. Suzuki
{"title":"一个20MHz 32b流水线CMOS图像处理器","authors":"A. Kanuma, M. Noda, H. Nihira, T. Yaguchi, N. Ikumi, C. Hori, M. Sugai, K. Suzuki","doi":"10.1109/ISSCC.1986.1156909","DOIUrl":null,"url":null,"abstract":"A 32b image processor with writable control stores that can process a 1024-point complex FFT in 1ms, has been developed. This paper will report on features which include fabrication in 1.2μm N-well CMOS, use of double layer metal technology and the integration of 170K transistors. Dissipation is 750mw at 5V.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A 20MHz 32b pipelined CMOS image processor\",\"authors\":\"A. Kanuma, M. Noda, H. Nihira, T. Yaguchi, N. Ikumi, C. Hori, M. Sugai, K. Suzuki\",\"doi\":\"10.1109/ISSCC.1986.1156909\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 32b image processor with writable control stores that can process a 1024-point complex FFT in 1ms, has been developed. This paper will report on features which include fabrication in 1.2μm N-well CMOS, use of double layer metal technology and the integration of 170K transistors. Dissipation is 750mw at 5V.\",\"PeriodicalId\":440688,\"journal\":{\"name\":\"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"34 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1986.1156909\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1986.1156909","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 32b image processor with writable control stores that can process a 1024-point complex FFT in 1ms, has been developed. This paper will report on features which include fabrication in 1.2μm N-well CMOS, use of double layer metal technology and the integration of 170K transistors. Dissipation is 750mw at 5V.