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1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

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Yield statistics for large area ICs 大面积集成电路的产率统计
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156918
C. Stapper
{"title":"Yield statistics for large area ICs","authors":"C. Stapper","doi":"10.1109/ISSCC.1986.1156918","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156918","url":null,"abstract":"This report will cover an examination of Poisson statistics and their inadequacy to represent defects in large area chips on a wafer. Measurements of defects will be cited and the consequences on redundancy methods will be discussed.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121482960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A digital audio filter using semi-automated design 采用半自动化设计的数字音频滤波器
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156986
J. van Ginderdeuren, H. de Man, A. Delaruelle, H. Wyngaert
{"title":"A digital audio filter using semi-automated design","authors":"J. van Ginderdeuren, H. de Man, A. Delaruelle, H. Wyngaert","doi":"10.1109/ISSCC.1986.1156986","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156986","url":null,"abstract":"A digital audio filter set with a SNR of 100dB, containing an offset filter, graphic equalizer sections and a scratch filter will be reported. Using semi-automatic design a chip area of 24.3mm2in 6μm NMOS was obtained.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131296110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 4Mb DRAM with cross point trench transistor cell 带有交叉点沟槽晶体管单元的4Mb DRAM
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156951
A. Shah, Chu Wang, R. Womack, J. Gallia, H. Shichijo, H. Davis, M. Elahy, S. Banerjee, G. Pollack, W. Richardson, D. Bordelon, S. Malhi, C. Pilch, B. Tran, P. Chatterjee
{"title":"A 4Mb DRAM with cross point trench transistor cell","authors":"A. Shah, Chu Wang, R. Womack, J. Gallia, H. Shichijo, H. Davis, M. Elahy, S. Banerjee, G. Pollack, W. Richardson, D. Bordelon, S. Malhi, C. Pilch, B. Tran, P. Chatterjee","doi":"10.1109/ISSCC.1986.1156951","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156951","url":null,"abstract":"This report will describe the design of a 9.8mm×10.2mm 1MW×4b DRAM fabricated in a 1μm double-level metal CMOS technology featuring trench-transistor cells measuring 9μm2. Row and static column access times are 170ns and 30ns, respectively.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XXIX 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129240559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Application-specific memory designs and their reality 特定于应用程序的内存设计及其现实
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156922
K. O'Connor
{"title":"Application-specific memory designs and their reality","authors":"K. O'Connor","doi":"10.1109/ISSCC.1986.1156922","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156922","url":null,"abstract":"With the rapid decrease in device dimensions and the resulting density and performance inprovements, designers can include significant amounts of memory within a logic circuit. Conventional memories have absorbed specialized logic functions to satisfy system design requirements. Video DRAMs, multiported and embedded SRAMs, digital TV CCDs and encryption EPROMs are current examples of devices exploring this avenue. Not all ventures are likely to succeed. The panel will address issues which will influence this success or failure, Not only will implementation aspects be probed, but panelists will attempt to contrast cost effectiveness of approaches, current and future market directions, testability concerns, and the future systems potential of application specific memories.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114409763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS two-dimensional digital filter for TV pictures 用于电视图像的CMOS二维数字滤波器
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156998
B. Zehner, H. Mattausch, R. Tielert, H.-J. Graller
{"title":"A CMOS two-dimensional digital filter for TV pictures","authors":"B. Zehner, H. Mattausch, R. Tielert, H.-J. Graller","doi":"10.1109/ISSCC.1986.1156998","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156998","url":null,"abstract":"Two-dimensional filtering, achieved by the design of a 22MHz IC, incorporating a resettable FIFO memory as a flexible delay unit, will be reported. The chip was implemented with 80K transistors in 2μm double-well CMOS.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121768967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Digital error correction to increase speed of successive approximation 数字误差校正，提高逐次逼近的速度
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156996
K. Bacrania
{"title":"Digital error correction to increase speed of successive approximation","authors":"K. Bacrania","doi":"10.1109/ISSCC.1986.1156996","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156996","url":null,"abstract":"A digital correction procedure that reduces the conversion time of a standard 12b A/D converter from 12μs to 7μs with but a 15% increase in die area will be presented.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"208 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122450356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A multistage delta-sigma modulator without double integration loop 无双积分回路的多级δ - σ调制器
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1157015
Toshio Hayashi, Y. Inabe, Kuniharu Uchimura, Tadakatsu Kimura
{"title":"A multistage delta-sigma modulator without double integration loop","authors":"Toshio Hayashi, Y. Inabe, Kuniharu Uchimura, Tadakatsu Kimura","doi":"10.1109/ISSCC.1986.1157015","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1157015","url":null,"abstract":"A delta-sigma modulator using two interleaved single integration loops to reduce quantization noise by 20dB will be described. The technique avoids the instability of a double integration loop and demonstrates 14b resolution. A 1.5μm CMOS IC operates from a single 5V supply.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117191813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 126
An analog front end for 2400b/s split-band full-duplex modems 模拟前端2400b/s分带全双工调制解调器
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156914
K. Yamamoto, H. Ohtake, J. Maruyama
{"title":"An analog front end for 2400b/s split-band full-duplex modems","authors":"K. Yamamoto, H. Ohtake, J. Maruyama","doi":"10.1109/ISSCC.1986.1156914","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156914","url":null,"abstract":"A single chip analog front end for 1200 and 2400b/s modems that includes A/D and D/A converters, processor interfaces, 50 poles of filtering and equalization, tone generators, and a call progress detection filter, will be discribed. A 5μm CMOS implementation requires a die area of 6.5×6.37mm2.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126301159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 32b floating point CMOS digital signal processor 32b浮点CMOS数字信号处理器
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156980
Y. Kawakami, H. Tanaka, T. Nukiyama, M. Yoshida, T. Nishitani, I. Kuroda, M. Araki, T. Hoshi, A. Nakajima
{"title":"A 32b floating point CMOS digital signal processor","authors":"Y. Kawakami, H. Tanaka, T. Nukiyama, M. Yoshida, T. Nishitani, I. Kuroda, M. Araki, T. Hoshi, A. Nakajima","doi":"10.1109/ISSCC.1986.1156980","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156980","url":null,"abstract":"A 1.5μm CMOS digital signal processor with 150ns instruction cycle time will be reported. The chip contains a 32b floating point parallel multiplier and a 55b floating point ALU. The IC contains 370K transistors.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122299253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 36/72b CMOS micro-mainframe chip set 36/72b CMOS微型主机芯片组
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156955
D. Fier, R. Caulk, P. Torgerson, D. Breid, R. Bradley, K. LeClair
{"title":"A 36/72b CMOS micro-mainframe chip set","authors":"D. Fier, R. Caulk, P. Torgerson, D. Breid, R. Bradley, K. LeClair","doi":"10.1109/ISSCC.1986.1156955","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156955","url":null,"abstract":"A six-chip processor set with mainframe compatible instructions, containing 786,000 transistors, fabricated with a1.2/μm double-layer metal technology, will be described. The chip set can be configured to operate from 0.4 to 1.5MIPS.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128542203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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