带有交叉点沟槽晶体管单元的4Mb DRAM

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1986.1156951

A. Shah, Chu Wang, R. Womack, J. Gallia, H. Shichijo, H. Davis, M. Elahy, S. Banerjee, G. Pollack, W. Richardson, D. Bordelon, S. Malhi, C. Pilch, B. Tran, P. Chatterjee

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引用次数: 27

摘要

本报告将介绍采用1μm双级金属CMOS技术制造的9.8mm×10.2mm 1MW×4b DRAM的设计，其槽型晶体管单元尺寸为9μm2。行访问时间和静态列访问时间分别为170ns和30ns。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 4Mb DRAM with cross point trench transistor cell

This report will describe the design of a 9.8mm×10.2mm 1MW×4b DRAM fabricated in a 1μm double-level metal CMOS technology featuring trench-transistor cells measuring 9μm2. Row and static column access times are 170ns and 30ns, respectively.

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来源期刊

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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