D. Fier, R. Caulk, P. Torgerson, D. Breid, R. Bradley, K. LeClair
{"title":"36/72b CMOS微型主机芯片组","authors":"D. Fier, R. Caulk, P. Torgerson, D. Breid, R. Bradley, K. LeClair","doi":"10.1109/ISSCC.1986.1156955","DOIUrl":null,"url":null,"abstract":"A six-chip processor set with mainframe compatible instructions, containing 786,000 transistors, fabricated with a1.2/μm double-layer metal technology, will be described. The chip set can be configured to operate from 0.4 to 1.5MIPS.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A 36/72b CMOS micro-mainframe chip set\",\"authors\":\"D. Fier, R. Caulk, P. Torgerson, D. Breid, R. Bradley, K. LeClair\",\"doi\":\"10.1109/ISSCC.1986.1156955\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A six-chip processor set with mainframe compatible instructions, containing 786,000 transistors, fabricated with a1.2/μm double-layer metal technology, will be described. The chip set can be configured to operate from 0.4 to 1.5MIPS.\",\"PeriodicalId\":440688,\"journal\":{\"name\":\"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1986.1156955\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1986.1156955","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A six-chip processor set with mainframe compatible instructions, containing 786,000 transistors, fabricated with a1.2/μm double-layer metal technology, will be described. The chip set can be configured to operate from 0.4 to 1.5MIPS.