M. Yoshimoto, S. Nakagawa, K. Murakami, S. Asai, Y. Akasaka, Y. Nakajima, Y. Horiba
{"title":"一种使用自适应滤波对复合电视信号进行解码的数字处理器","authors":"M. Yoshimoto, S. Nakagawa, K. Murakami, S. Asai, Y. Akasaka, Y. Nakajima, Y. Horiba","doi":"10.1109/ISSCC.1986.1157019","DOIUrl":null,"url":null,"abstract":"The adaptive separation of color TV signals into luminance/ chrominance components and color compensation using an 8b pipelined signal processor with a 2-line store will be described. A 2μm CMOS IC was designed for implementation with an 18K serial memory operated at 17.7MHz. Dissipation is 450mW.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1986-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A digital processor for decoding of composite TV signals using adaptive filtering\",\"authors\":\"M. Yoshimoto, S. Nakagawa, K. Murakami, S. Asai, Y. Akasaka, Y. Nakajima, Y. Horiba\",\"doi\":\"10.1109/ISSCC.1986.1157019\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The adaptive separation of color TV signals into luminance/ chrominance components and color compensation using an 8b pipelined signal processor with a 2-line store will be described. A 2μm CMOS IC was designed for implementation with an 18K serial memory operated at 17.7MHz. Dissipation is 450mW.\",\"PeriodicalId\":440688,\"journal\":{\"name\":\"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1986-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1986.1157019\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1986.1157019","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A digital processor for decoding of composite TV signals using adaptive filtering
The adaptive separation of color TV signals into luminance/ chrominance components and color compensation using an 8b pipelined signal processor with a 2-line store will be described. A 2μm CMOS IC was designed for implementation with an 18K serial memory operated at 17.7MHz. Dissipation is 450mW.