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1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

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A pattern matching processor array with defect tolerance 一种具有缺陷容忍度的模式匹配处理器阵列
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156985
T. Kawada, Y. Takahashi, N. Tsuda, M. Waki, N. Hagiwara
{"title":"A pattern matching processor array with defect tolerance","authors":"T. Kawada, Y. Takahashi, N. Tsuda, M. Waki, N. Hagiwara","doi":"10.1109/ISSCC.1986.1156985","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156985","url":null,"abstract":"A 16b processor chip with sorter and 32Kb dictionary RAM has been developed for hand-printed Kanji character recognition. This paper will describe the design techniques used to achieve defect tolerance in the memory and logic blocks. A 18.5×20.5mm2chip contains 460,000 transistors using a 3μm double metal CMOS technology.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129212745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 4ns access time 4K × 4 ECL RAM 一个4ns访问时间的4K × 4 ECL RAM
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156940
M. Arimura, M. Nakame, T. Tashiro, S. Ohi, T. Kamiya, S. Kishi, Y. Minato, J. Nokubo, T. Tamura
{"title":"A 4ns access time 4K × 4 ECL RAM","authors":"M. Arimura, M. Nakame, T. Tashiro, S. Ohi, T. Kamiya, S. Kishi, Y. Minato, J. Nokubo, T. Tamura","doi":"10.1109/ISSCC.1986.1156940","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156940","url":null,"abstract":"","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116308081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A flat-panel display control IC with 150V drivers 一种带150V驱动器的平板显示控制IC
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/isscc.1986.1156908
T. Okabe, M. Kimura, I. Shimizu, Y. Nagai, K. Hoya
{"title":"A flat-panel display control IC with 150V drivers","authors":"T. Okabe, M. Kimura, I. Shimizu, Y. Nagai, K. Hoya","doi":"10.1109/isscc.1986.1156908","DOIUrl":"https://doi.org/10.1109/isscc.1986.1156908","url":null,"abstract":"This report will cover the development of a 32-channel flat-panel display control with 150V push-pull operating at 7MHz. A junction isolated process has been used to produce the device.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"6 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113955645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CMOS/bipolar circuits for 60MHz digital processing CMOS/双极电路用于60MHz数字处理
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156892
T. Hotta, I. Masuda, H. Maejima, A. Hotta
{"title":"CMOS/bipolar circuits for 60MHz digital processing","authors":"T. Hotta, I. Masuda, H. Maejima, A. Hotta","doi":"10.1109/ISSCC.1986.1156892","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156892","url":null,"abstract":"CMOS/bipolar circuits with 0.8V internal swing for use in 60MHz digital processing will be discussed, A 7.2ns carry propagation delay time and a 17ns access time have been achieved in a 32b adder and a 128Kb ROM, respectively.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124119159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 25MHz thermally-based RMS-to-DC converter 25MHz基于热的RMS-to-DC转换器
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156956
J. Williams, T. Longman
{"title":"A 25MHz thermally-based RMS-to-DC converter","authors":"J. Williams, T. Longman","doi":"10.1109/ISSCC.1986.1156956","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156956","url":null,"abstract":"This paper will describe a thermally-based rms-to-dc converter with 1% accuracy for 25MHz bandwidth inputs.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126380210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Reduced instruction set computers 精简指令集计算机
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156895
R. Katz
{"title":"Reduced instruction set computers","authors":"R. Katz","doi":"10.1109/ISSCC.1986.1156895","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156895","url":null,"abstract":"The infulential computer architects believe that conventional microprocessor architectures have reached a performance limit and represent a dead end in processor evolution. A new approach, the Reduced Instruction Set Computer (RISC) has emerged from research laboratories and is poised to enter the marketplace. RISC processors achieve performance by a careful selection and streamlining of the instruction set making possible a high-performance pipelined implementation. But not all microprocessor designers agree with the RISC approach. Panelists will address the future role of RISC and whether it will displace conventional architectures in the next generation. To be debated is whether or not there is a need for a new architecture, even if technically superior, in the existing volume marketplace. Possibly, as technology advancements appear, the mood could change during the next five years.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133340369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS macro array CMOS宏阵列
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156974
Y. Kitamura, K. Furuki, M. Minowa, T. Yamada
{"title":"A CMOS macro array","authors":"Y. Kitamura, K. Furuki, M. Minowa, T. Yamada","doi":"10.1109/ISSCC.1986.1156974","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156974","url":null,"abstract":"A 1.6μm, 2-level netal, N-well logic array, containing gate array and PLA cells will be reported. The performance and area for a 16b ALU and 16b up-down counter will be compared with a conventional gate array implementation.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124172251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 25ns 256K CMOS SRAM 25ns 256K CMOS SRAM
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156929
M. Honda, K. Kondou, H. Mitani, T. Kimura, S. Koshimaru, Y. Nagahashi, M. Tameda
{"title":"A 25ns 256K CMOS SRAM","authors":"M. Honda, K. Kondou, H. Mitani, T. Kimura, S. Koshimaru, Y. Nagahashi, M. Tameda","doi":"10.1109/ISSCC.1986.1156929","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156929","url":null,"abstract":"","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124573294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 1280 × 980 pixel CCD image sensor 一个1280 × 980像素的CCD图像传感器
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156937
I. Akiyama, T. Tanaka, E. Oda, T. Kamata, K. Masubuchi, K. Arai, Y. Ishihara
{"title":"A 1280 × 980 pixel CCD image sensor","authors":"I. Akiyama, T. Tanaka, E. Oda, T. Kamata, K. Masubuchi, K. Arai, Y. Ishihara","doi":"10.1109/ISSCC.1986.1156937","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156937","url":null,"abstract":"An interline-transfer CCD image sensor with 1280(H)× 970(V) pixels that has been developed for a TV camera will be presented. The device, designed for high definition TV, has a 48dB SNR.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123957607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A bipolar opamp with a noise resistance of less than 50ω 抗噪声小于50ω的双极运放
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156941
G. Erdi, Y. Cakhnokhi
{"title":"A bipolar opamp with a noise resistance of less than 50ω","authors":"G. Erdi, Y. Cakhnokhi","doi":"10.1109/ISSCC.1986.1156941","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156941","url":null,"abstract":"This paper will cover the design of an opamp with input noise resistance of less than 50Ω. The offset voltage and bias current are internally trimmed to 50μV and 15nA, respectively. The slew rate is 13V/μs.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XXIX 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129834718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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