CMOS宏阵列

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1986.1156974

Y. Kitamura, K. Furuki, M. Minowa, T. Yamada

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引用次数: 1

摘要

一种1.6μm, 2电平，n阱逻辑阵列，包含门阵列和PLA单元。16b ALU和16b上下计数器的性能和面积将与传统的门阵列实现进行比较。

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A CMOS macro array

A 1.6μm, 2-level netal, N-well logic array, containing gate array and PLA cells will be reported. The performance and area for a 16b ALU and 16b up-down counter will be compared with a conventional gate array implementation.

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来源期刊

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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