1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

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An ECL 2.8ns 16K RAM with 1.2K logic gate array ECL 2.8ns 16K RAM, 1.2K逻辑门阵列
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156902
Y. Sugo, M. Tanaka, Y. Mafune, T. Takeshima, S. Aihara, K. Tanaka
{"title":"An ECL 2.8ns 16K RAM with 1.2K logic gate array","authors":"Y. Sugo, M. Tanaka, Y. Mafune, T. Takeshima, S. Aihara, K. Tanaka","doi":"10.1109/ISSCC.1986.1156902","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156902","url":null,"abstract":"AN ECL 16Kb bipolar SRAM with 1248 logic gates in an array using a U-groove IOP-I1 (Isolation by Oxide and Polysilicon) isolation, a 1.0pm design rule and three layers of metalization, will be described. The RAM has a typical access time of 2.8ns, and has a typical write pulse width of 2.5ns with power dissipation of 4.4W. The gate has a basic propagation delay time of 280ps with a power dissipation of 2.2mWl gate. The die is housed in a 180-pin flat package. Examples of the switching waveform of the RAM access time and ring oscillator (9 OR-gates) are shown in Figures 1 and 2. The elimination of on-board interconnects between the RAM and logic devices, which often become a critical path in a conventional system, improves clock cycle time in this development. Since on-chip wires between the RAM and logic circuit do not require high power buffers, large bitwidth organization such as 64b of RAM is possible on the chip, with small power dissipation. The gate array consists of 1120 internal gates and 128 output gates. Each gate has a potential 3-input OR/NOR configuration. The internal gates are used for input buffer gates and internal circuits. Internal gates have a low logic swing (500mV) to reduce delay time. Internal gates are divided into 280 macros. Each macro has 4 gates and 36 x 40 wiring channels. Size of the macro is 265.5/..lm x 292.5pm. The 280 macros are arranged in 28 rows by 10 columns and lie between two memory arrays.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122351624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
MOS pass transistors with reduced transient error charge 具有减少瞬态误差电荷的MOS通型晶体管
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1157005
J. Kuo, C. Fu, D. Dameron, R. Dutton, B. Wooley
{"title":"MOS pass transistors with reduced transient error charge","authors":"J. Kuo, C. Fu, D. Dameron, R. Dutton, B. Wooley","doi":"10.1109/ISSCC.1986.1157005","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1157005","url":null,"abstract":"A two-lump model, developed for MOS pass transistors, to represent the turnoff transient error charge, will be described. Reduction of this error by 90% will be cited for a circular transistor structure.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123724100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 0.9ns ECL 16 × 4 register file 一个0.9ns ECL 16 × 4寄存器文件
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156943
D. Chang, C. Schmitz, H. Hingarh, G. Bakker
{"title":"A 0.9ns ECL 16 × 4 register file","authors":"D. Chang, C. Schmitz, H. Hingarh, G. Bakker","doi":"10.1109/ISSCC.1986.1156943","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156943","url":null,"abstract":"This paper will describe a 16×4 ECL register file featuring an address access time of 0.9ns and power dissipation of 400mW. Performance has been achieved by using a fully self-aligned poly bipolar technology with trench isolation.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125406115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Two 64K CMOS SRAMs with 13ns access time 两个64K CMOS ram,访问时间为13ns
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156991
S. Flannagan, P. Reed, P. Voss, S. Nogle, B. Simon, D. Sheng, R. Kung, J. Barnes
{"title":"Two 64K CMOS SRAMs with 13ns access time","authors":"S. Flannagan, P. Reed, P. Voss, S. Nogle, B. Simon, D. Sheng, R. Kung, J. Barnes","doi":"10.1109/ISSCC.1986.1156991","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156991","url":null,"abstract":"This report will cover the development of 64K×1 and 16K×4 CMOS SRAMS with access times of 13ns and power dissipation of 60mW at 10MHz. A 1.5μm double-metal, double-poly process was used. Array archtiecture allowing short lines, high-gain data path and asynchronous circuit techniques will be described.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121684362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 4K GaAs bipolar gate array 一种4K GaAs双极门阵列
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156965
Han-Tzong Yuan, J. Delaney, Hung-Dah Shin, L. Tran
{"title":"A 4K GaAs bipolar gate array","authors":"Han-Tzong Yuan, J. Delaney, Hung-Dah Shin, L. Tran","doi":"10.1109/ISSCC.1986.1156965","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156965","url":null,"abstract":"A 4K GaAs gate array providing propagation delays in 32b shift registers of 230 and 550ps at 4 and 1mW dissipation for a fanout of four will be described.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123886041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A CAD-oriented non-quasistatic MOSFET model for transient analysis 面向cad的非准静态MOSFET模型用于瞬态分析
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156979
C. Turchetti, G. Masetti, P. Mancini
{"title":"A CAD-oriented non-quasistatic MOSFET model for transient analysis","authors":"C. Turchetti, G. Masetti, P. Mancini","doi":"10.1109/ISSCC.1986.1156979","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156979","url":null,"abstract":"A comparison of the step response of a MOSFET predicted by a simplified non-quasistatic model with the results of detailed numerical simulations will be presented. The sources of error will be detailed. The model afforded greater efficiency in circuit simulation.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"282 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133263617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 65 ns CMOS 1Mb DRAM 一个65ns CMOS 1Mb DRAM
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156984
C. Webb, R. Creek, W. Holt, G. King, I. Young
{"title":"A 65 ns CMOS 1Mb DRAM","authors":"C. Webb, R. Creek, W. Holt, G. King, I. Young","doi":"10.1109/ISSCC.1986.1156984","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156984","url":null,"abstract":"This paper will cover a 5.3×9.6 mm CMOS 1Mb DRAM using a 28.5μm2/l transistor cell with a self-aligned contact. The memory array has been placed in an N-well reducing the soft error rate below 1000FITs without die coat.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"49 11-12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114021180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
73ps si bipolar ECL circuits 73ps双极ECL电路
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156926
D. Tang, Guann-Pyng Li, C. Chuang, D. Danner, M. Ketchen, J. Mauer, M. Smyth, M. Manny, J. Cressler, B. Ginsberg, E. Petrillo, T. Ning, C. Hu, H. Pak
{"title":"73ps si bipolar ECL circuits","authors":"D. Tang, Guann-Pyng Li, C. Chuang, D. Danner, M. Ketchen, J. Mauer, M. Smyth, M. Manny, J. Cressler, B. Ginsberg, E. Petrillo, T. Ning, C. Hu, H. Pak","doi":"10.1109/ISSCC.1986.1156926","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156926","url":null,"abstract":"THIS PAPER will cover 1.2pm Si-bipolar Emitter-Couple-Logic circuits with a minimum gate delay of 73ps’. The circuits were fabricated with bipolar technology (Fi ure 1) featuring poly-base self-alignment, polyemitter shallow r o f i l j , walled-emitter together with silicon-filled trench isolation and polysilicon resistors. This technology was also used to implement non-threshold logic (NTL) circuits with I/I resistors. The NTL ring oscillator gate delay was found to be 44ps.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"324 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115567799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A quad CMOS single-supply opamp with rail-to rail output swing 具有轨到轨输出摆幅的四路CMOS单电源运放
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156957
D. Monticelli
{"title":"A quad CMOS single-supply opamp with rail-to rail output swing","authors":"D. Monticelli","doi":"10.1109/ISSCC.1986.1156957","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156957","url":null,"abstract":"A report on a quad opamp built in a conventional 4μm, double-poly CMOS process, will be presented. It operates on a 5V supply and achieves rail-to-rail output. Performance is comparable to that of bipolar opamps.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114513406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A CMOS slope adaptive delta modulator 一种CMOS斜率自适应增量调制器
1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156999
J. Scott, Wai L. Lee, C. Giancario, C. Sodini
{"title":"A CMOS slope adaptive delta modulator","authors":"J. Scott, Wai L. Lee, C. Giancario, C. Sodini","doi":"10.1109/ISSCC.1986.1156999","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156999","url":null,"abstract":"A slope adaptive A/D converter that reduces quantization noise through oversampling and feedback will be presented. A dynamic range of 90dB in the audio band, 15b resolution and total harmonic distortion of 0.17% at 1kHz has been achieved using a 3.5μm process.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115270777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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