An ECL 2.8ns 16K RAM with 1.2K logic gate array

AN ECL 16Kb bipolar SRAM with 1248 logic gates in an array using a U-groove IOP-I1 (Isolation by Oxide and Polysilicon) isolation, a 1.0pm design rule and three layers of metalization, will be described. The RAM has a typical access time of 2.8ns, and has a typical write pulse width of 2.5ns with power dissipation of 4.4W. The gate has a basic propagation delay time of 280ps with a power dissipation of 2.2mWl gate. The die is housed in a 180-pin flat package. Examples of the switching waveform of the RAM access time and ring oscillator (9 OR-gates) are shown in Figures 1 and 2. The elimination of on-board interconnects between the RAM and logic devices, which often become a critical path in a conventional system, improves clock cycle time in this development. Since on-chip wires between the RAM and logic circuit do not require high power buffers, large bitwidth organization such as 64b of RAM is possible on the chip, with small power dissipation. The gate array consists of 1120 internal gates and 128 output gates. Each gate has a potential 3-input OR/NOR configuration. The internal gates are used for input buffer gates and internal circuits. Internal gates have a low logic swing (500mV) to reduce delay time. Internal gates are divided into 280 macros. Each macro has 4 gates and 36 x 40 wiring channels. Size of the macro is 265.5/..lm x 292.5pm. The 280 macros are arranged in 28 rows by 10 columns and lie between two memory arrays.