73ps si bipolar ECL circuits

Abstract

THIS PAPER will cover 1.2pm Si-bipolar Emitter-Couple-Logic circuits with a minimum gate delay of 73ps’. The circuits were fabricated with bipolar technology (Fi ure 1) featuring poly-base self-alignment, polyemitter shallow r o f i l j , walled-emitter together with silicon-filled trench isolation and polysilicon resistors. This technology was also used to implement non-threshold logic (NTL) circuits with I/I resistors. The NTL ring oscillator gate delay was found to be 44ps.