Two 64K CMOS SRAMs with 13ns access time

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1986.1156991

S. Flannagan, P. Reed, P. Voss, S. Nogle, B. Simon, D. Sheng, R. Kung, J. Barnes

引用次数: 4

Abstract

This report will cover the development of 64K×1 and 16K×4 CMOS SRAMS with access times of 13ns and power dissipation of 60mW at 10MHz. A 1.5μm double-metal, double-poly process was used. Array archtiecture allowing short lines, high-gain data path and asynchronous circuit techniques will be described.

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两个64K CMOS ram，访问时间为13ns

本报告将介绍64K×1和16K×4 CMOS sram的开发，其访问时间为13ns, 10MHz时功耗为60mW。采用1.5μm双金属双聚工艺。阵列架构允许短线，高增益的数据路径和异步电路技术将被描述。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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