约瑟夫森阈值逻辑中的4b × 4b乘法器和3b计数器

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1986.1156938

Y. Hatano, Y. Harada, K. Yamashita, U. Kawabe

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引用次数: 7

摘要

本文将报道一种4×4b并行乘法器的开发，其携带对携带延迟时间为279ps，并在约瑟夫森结技术中实现了一个工作在2.2 GHz的3b二进制计数器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 4b × 4b multiplier and 3b counter in Josephson threshold logic

This Paper will report on the development of a 4×4b parallel multiplier with a carry-to-carry delay time of 279ps and a 3b binary counter operating at 2.2 GHz implemented in Josephson junction technology.

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1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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