1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献_第8页

Architecture for DSP VLSI DSP VLSI体系结构

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156931

S. Magar

引用次数: 0

A 13GHz GaAs dynamic frequency divider and prescaler IC 一种13GHz GaAs动态分频器和预分频器集成电路

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156887

T. Sugeta, K. Osafune, K. Ohwada

引用次数: 0

A realtime image processing chip set 一种实时图像处理芯片组

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1157001

P. Ruetz, R. Brodersen

引用次数: 24

A VLSI chip set for an integrated text and graphics video subsystem 一种集成文本和图形视频子系统的VLSI芯片组

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156992

W. Blake, P. English, N. Forrester, T. Furlong, R. Rose, R. Watson

引用次数: 0

A bipolar-CMOS field programmable array 一种双极cmos现场可编程阵列

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156973

R. Murphy, T. McFarlane, C. Sporck, K. Rapp, R. Smolen, W. Collins, R. Ramus, M. Millhollan, J. Readdie

引用次数: 6

An 8b 250MHz A/D converter 8b 250MHz A/D转换器

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156903

B. Peetz, B. Hamilton, J. Kang

引用次数: 5

An 80MHz 8b CMOS D/A converter 80MHz 8b CMOS D/A转换器

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1157020

T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, Y. Horiba

引用次数: 4

A 1Mb DRAM with 33MHz serial I/O ports 带有33MHz串行I/O端口的1Mb DRAM

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1157012

K. Ohta, H. Kawai, M. Fujii, S. Ueda, Y. Furuta

{"title":"A 1Mb DRAM with 33MHz serial I/O ports","authors":"K. Ohta, H. Kawai, M. Fujii, S. Ueda, Y. Furuta","doi":"10.1109/ISSCC.1986.1157012","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1157012","url":null,"abstract":"THIS PAPER WILL DESCRIBE a 1Mb image memory, 256k x 4 DRAM with 30ns bit rate serial 1/0 ports with special features for TV or VCR image display applications. In this development, 4b wide data are shifted into 4 sets of 8 b shift registers, loaded from the DRAM to other 4 sets of 8b shift registers and shifted out through serial ports. These operations are performed under 33MHz clock without any idle time. One field of a color TV signal has 256k x 8b, so that only two chips of this memory are enough to store it. A block diagram of the memory is shown in Figure 1. The DRAM block is constructed with 512 rows and 2,048 columns. 2,048 columns are divided into 4 groups, and each group has 64 x 8b columns. Serial data handling block is constructed with four sets of 8 I/O selectors, 8b serialin and serial-out registers. Figure 2 shows the timing diagram of this memory. In the write cycle, input data are shifted into an 8 b serial-in register by synchronizing the rising edge ofSIC clock through data input pins, D l 1 to D14. At the falling edge of WS clock, 32b data in four 8b serial-in re&ers are transfered to 32b data registers. And at the falling edge of WE clock, 32b data go through I/O selectors and to 32b memory cells which have been selected and activated by IS &dress pins (A0 A14), a chip select pin (CS), and a chip enable pin (CE). In the read mode, readout data from the selected address are sensed, go through I/O selectors and are loaded on four 8b serial out registers at the falling edge of RS clock. Data from the serial out registers are shifted out serially at every rising edge of SOC clock through data","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122648831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A 15Mb/s data separator and write compensation circuit for Winchester disk drives 用于温彻斯特磁盘驱动器的15Mb/s数据分离器和写入补偿电路

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156882

J. Kellis, S. Mehrotra

引用次数: 5

A basic-cell buffer 440K-transistor CMOS masterslice 基本单元缓冲440k晶体管CMOS主片

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1986.1156920

T. Arakawa, M. Ueda, Y. Saito, T. Fujimura, S. Asai, M. Terai, Y. Akasaka, Y. Kuramitsu

引用次数: 4