基本单元缓冲440k晶体管CMOS主片

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1986.1156920

T. Arakawa, M. Ueda, Y. Saito, T. Fujimura, S. Asai, M. Terai, Y. Akasaka, Y. Kuramitsu

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引用次数: 4

摘要

将报道在12.7×11.96mm2chip上包含437,976个晶体管的主片，并采用无固定路由轨道和专用缓冲区的栅极隔离概念。该母片采用1.3μm CMOS工艺制备。利用该阵列实现了一个13MHz传真处理器。

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A basic-cell buffer 440K-transistor CMOS masterslice

A masterslice containing 437,976 transistors on a 12.7×11.96mm2chip and employing a gate-isolation concept with no fixed routing tracks and no dedicated buffers, will be reported. The masterslice has been fabricated in 1.3μm CMOS technology. A 13MHz facsimile processor has been implemented using this array.

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来源期刊

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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