{"title":"DSP VLSI体系结构","authors":"S. Magar","doi":"10.1109/ISSCC.1986.1156931","DOIUrl":null,"url":null,"abstract":"AS CMOS technology scales to 1μm, it is becoming possible to integrate more than 500K transistors on a processor-like chip. At this point, various digital signal processing (DSP) chip architecture approaches need to be re-examined to enable VLSI designers to obtain on optimal solution for system designers in terms of performance, power, cost, flexibility and development time. The panel will explore and debate several DSP architectural options available to VLSI designers, such as single-processor, systolic arrays, parallel processors, customs, etc.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Architecture for DSP VLSI\",\"authors\":\"S. Magar\",\"doi\":\"10.1109/ISSCC.1986.1156931\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"AS CMOS technology scales to 1μm, it is becoming possible to integrate more than 500K transistors on a processor-like chip. At this point, various digital signal processing (DSP) chip architecture approaches need to be re-examined to enable VLSI designers to obtain on optimal solution for system designers in terms of performance, power, cost, flexibility and development time. The panel will explore and debate several DSP architectural options available to VLSI designers, such as single-processor, systolic arrays, parallel processors, customs, etc.\",\"PeriodicalId\":440688,\"journal\":{\"name\":\"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1986.1156931\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1986.1156931","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
AS CMOS technology scales to 1μm, it is becoming possible to integrate more than 500K transistors on a processor-like chip. At this point, various digital signal processing (DSP) chip architecture approaches need to be re-examined to enable VLSI designers to obtain on optimal solution for system designers in terms of performance, power, cost, flexibility and development time. The panel will explore and debate several DSP architectural options available to VLSI designers, such as single-processor, systolic arrays, parallel processors, customs, etc.
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