R. Swartz, A. Voshchenkov, G. Chin, S. N. Finegan, M. Lau, M. Morris, V. Archer, P. Ko
{"title":"A 2Gb/s silicon NMOS laser driver","authors":"R. Swartz, A. Voshchenkov, G. Chin, S. N. Finegan, M. Lau, M. Morris, V. Archer, P. Ko","doi":"10.1109/ISSCC.1986.1156875","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156875","url":null,"abstract":"A laser driver IC fabricated in a 1μm gate NMOS process will be reported. Intended for use in optical communications, it has been operated at 2 Gb/s and at output levels of 200mA without detectable data error.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129496912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Fujii, S. Saito, Y. Okada, M. Sato, S. Sawada, S. Shinozaki, K. Natori, O. Ozawa
{"title":"A 50µA standby 1MW × 1b/256KW × 4b CMOS DRAM","authors":"S. Fujii, S. Saito, Y. Okada, M. Sato, S. Sawada, S. Shinozaki, K. Natori, O. Ozawa","doi":"10.1109/ISSCC.1986.1156942","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156942","url":null,"abstract":"A single mask set DRAM architecture with a 1MW×1b or 256KW×4b organization, selectable by bonding configurations, will be discussed. With a CMOS half Vcccc generator, a standby current of 50μA has been achieved. A triple layer polysilicon N-well measuring 3.24μm2has resulted in a chip size of 4.4×12.3mm2with an access time of 56ns.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117298849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 50Mb/s CMOS LED driver circuit","authors":"A. Fisher, N. Linde","doi":"10.1109/ISSCC.1986.1156949","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156949","url":null,"abstract":"An LED driver circuit for an optical transmitter has been designed in a 1.5μm digital CMOS technology. Featured are a 50MHz data scrambler, a trimmable temperature-compensated output current of between 50mA and 80mA and switching times of <2ns.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"20 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113981331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Kuroda, T. Kuriyama, Y. Matsuda, T. Kozono, S. Matsumoto, Y. Hiroshima, K. Horii
{"title":"A smear-suppressing CCD imager","authors":"T. Kuroda, T. Kuriyama, Y. Matsuda, T. Kozono, S. Matsumoto, Y. Hiroshima, K. Horii","doi":"10.1109/ISSCC.1986.1157017","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1157017","url":null,"abstract":"This report will describe a 502×600 element interline-transfer CCD imager which realizes a 100-fold reduction in smear level, through the use of a flared photodiode structure.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115184291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Kobayashi, K. Arimoto, Y. Ikeda, M. Hatanaka, K. Mashiko, M. Yamada
{"title":"A 47ns 64KW × 4b CMOS DRAM with relaxed timing requirements","authors":"T. Kobayashi, K. Arimoto, Y. Ikeda, M. Hatanaka, K. Mashiko, M. Yamada","doi":"10.1109/ISSCC.1986.1156944","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156944","url":null,"abstract":"A 256Kb DRAM which eliminates the positive-going RAS signal edge from the internal timing by a time-out function, will be reported. The access time is 47ns with predecoding, and power dissipation is 115mW at 200ns cycle time.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115215534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Buckley, S. Chen, J. Hilse, M. Homan, G. Machol, L. Pereira, J. Terry, G. Watanabe
{"title":"A bipolar 32b processor chip","authors":"F. Buckley, S. Chen, J. Hilse, M. Homan, G. Machol, L. Pereira, J. Terry, G. Watanabe","doi":"10.1109/ISSCC.1986.1156966","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156966","url":null,"abstract":"The architecture, circuitry, packaging and design of a 14×16mm 32b CPU chip dissipating 16W will be described. The chip, which has been built in a 2μm bipolar process with 8-level cascode ECL circuitry, executes a mainframe instruction set.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124910070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A monolithic data access and line interface chip for modems and PBX trunks","authors":"M. Snowden, S. Falater","doi":"10.1109/ISSCC.1986.1156916","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156916","url":null,"abstract":"A line interface circuit utilizing on-chip RF modulation to isolate capacitively up to 1500V on the line, and electrothermal methods to transfer supervisory information, will be described. The IC was fabricated in a 200V bipolar process.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129626968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Pendelton, S. Kong, E. Brown, F. Dunlap, C. Marino, D. Ungar, D. Patterson, D. Hodges
{"title":"A 32b microprocessor for Smalltalk","authors":"J. Pendelton, S. Kong, E. Brown, F. Dunlap, C. Marino, D. Ungar, D. Patterson, D. Hodges","doi":"10.1109/ISSCC.1986.1156983","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156983","url":null,"abstract":"A 32b microprocessor built specially to execute smalltalk will be presented. A 4μm NMOS implementation operates at 400ns per instruction and consists of 36K transistors in a die size of 320×432 mils.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128808665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Chan, J. Brown, R. Nijhuis, C. Rivadeneira, J. Struk
{"title":"A 3ns 32K bipolar RAM","authors":"Y. Chan, J. Brown, R. Nijhuis, C. Rivadeneira, J. Struk","doi":"10.1109/ISSCC.1986.1156896","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156896","url":null,"abstract":"A 3ns 32K bipolar SRAM with an unclamped complementary transistor switch memory cell, affording the advantages of 20%-30% smaller area, higher soft error immunity and improved leakage tolerance, will be described. A polysilicon trench isolation process with 1.5μm lithography provided a die area of 33.5mm2.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124523754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Pathak, H. Kurowski, R. Pugh, R. Shrivastava, F. Jenne
{"title":"A 19ns 250mW programmable logic device","authors":"J. Pathak, H. Kurowski, R. Pugh, R. Shrivastava, F. Jenne","doi":"10.1109/ISSCC.1986.1156928","DOIUrl":"https://doi.org/10.1109/ISSCC.1986.1156928","url":null,"abstract":"FAST PROGRAMMABLE LOGIC DEVICES are traditionally implemented in the bipolar fuse technology. Bipolar fuse technology satisfies the speed requirement of these devices, but has two major disadvantages: ( I ) significantly higher power consumption and, (2) fuse technology does not allow reprogrammability and 100% testability. High-speed CMOS technology along with the demonstrated reliability and reprogrammability of FAMOS devices is gaining momentum in high-speed programmable logic design. A 19ns, low-power 250mW, 44-input term and 132 product term programmable logic device using 1 . 2 ~ N-well CMOS EPROM technology will be described. The power is one fourth of equivalent bipolar parts. Both the N and P channel peripheral transistors use self-aligned, shallow-junction, lightlydoped drains (LDD). The LDD structure reduces overlap capacitance and minimizes hot electron injection. The programmable element is a two-transistor FAMOS cell optimized for speed and programmability; Figure 1. The cell size is 133p2. The programming characteristic is shown in Figure 2. The technology uses a back bias generator, which reduces the parasitic capacitance, improves field threshold for better programming and provides latch up immunity greater than 200mA. The die size is 3.lmm x 4.lmm; Figure 3. Typical propagation delay of 19ns and clock to output of lOns","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127206224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}