A 3ns 32K bipolar RAM

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1986.1156896

Y. Chan, J. Brown, R. Nijhuis, C. Rivadeneira, J. Struk

引用次数: 13

Abstract

A 3ns 32K bipolar SRAM with an unclamped complementary transistor switch memory cell, affording the advantages of 20%-30% smaller area, higher soft error immunity and improved leakage tolerance, will be described. A polysilicon trench isolation process with 1.5μm lithography provided a die area of 33.5mm2.

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3ns 32K双极RAM

本文将介绍一种3ns 32K双极SRAM，该SRAM采用无箝位互补晶体管开关存储单元，面积缩小20%-30%，具有更高的软误差抗扰度和改进的泄漏容限。采用1.5μm光刻工艺的多晶硅沟槽隔离工艺可提供33.5mm2的模具面积。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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